Ponències/Comunicacions de congressos
http://hdl.handle.net/2117/3095
Fri, 20 Apr 2018 09:56:49 GMT
20180420T09:56:49Z

A study into the feasibility of generic programming for the construction of complex software
http://hdl.handle.net/2117/116347
A study into the feasibility of generic programming for the construction of complex software
Caballé Llobet, Santiago; Xhafa Xhafa, Fatos
A high degree of abstraction and capacity for reuse can be obtained in software design through the use of Generic Programming (GP) concepts. Despite widespread use of GP in computing, some areas such as the construction of generic component libraries as the skeleton for complex computing systems with extensive domains have been neglected. Here we consider the design of a library of generic components based on the GP paradigm implemented with Java. Our aim is to investigate the feasibility of using GP paradigm in the construction of complex computer systems where the management of users interacting with the system and the optimisation of the system’s resources is required.
Mon, 16 Apr 2018 14:01:11 GMT
http://hdl.handle.net/2117/116347
20180416T14:01:11Z
Caballé Llobet, Santiago
Xhafa Xhafa, Fatos
A high degree of abstraction and capacity for reuse can be obtained in software design through the use of Generic Programming (GP) concepts. Despite widespread use of GP in computing, some areas such as the construction of generic component libraries as the skeleton for complex computing systems with extensive domains have been neglected. Here we consider the design of a library of generic components based on the GP paradigm implemented with Java. Our aim is to investigate the feasibility of using GP paradigm in the construction of complex computer systems where the management of users interacting with the system and the optimisation of the system’s resources is required.

Towards a generic platform for developing CSCL applications using Grid infrastructure
http://hdl.handle.net/2117/116250
Towards a generic platform for developing CSCL applications using Grid infrastructure
Caballé Llobet, Santiago; Xhafa Xhafa, Fatos; Daradoumis, Thanasis; Marques Puig, Joan Manuel
The goal of this paper is to explore the possibility of using CSCL componentbased software under a Grid infrastructure. The merge of these technologies represents an attractive, but probably quite laborious enterprise if we consider not only the benefits but also the barriers that we have to overcome. This work presents an attempt toward this direction by developing a generic platform of CSCL components and discussing the advantages that we could obtain if we adapted it to the Grid. We then propose a means that could make this adjustment possible due to the high degree of genericity that our library component is endowed with by being based on the generic programming paradigm. Finally, an application of our library is proposed both for validating the adequacy of the platform which it is based on and for indicating the possibilities gained by using it under the Grid.
Fri, 13 Apr 2018 12:05:39 GMT
http://hdl.handle.net/2117/116250
20180413T12:05:39Z
Caballé Llobet, Santiago
Xhafa Xhafa, Fatos
Daradoumis, Thanasis
Marques Puig, Joan Manuel
The goal of this paper is to explore the possibility of using CSCL componentbased software under a Grid infrastructure. The merge of these technologies represents an attractive, but probably quite laborious enterprise if we consider not only the benefits but also the barriers that we have to overcome. This work presents an attempt toward this direction by developing a generic platform of CSCL components and discussing the advantages that we could obtain if we adapted it to the Grid. We then propose a means that could make this adjustment possible due to the high degree of genericity that our library component is endowed with by being based on the generic programming paradigm. Finally, an application of our library is proposed both for validating the adequacy of the platform which it is based on and for indicating the possibilities gained by using it under the Grid.

A gridbased approach for processing group activity log files
http://hdl.handle.net/2117/116247
A gridbased approach for processing group activity log files
Xhafa Xhafa, Fatos; Caballé Llobet, Santiago; Daradoumis, Thanasis; Zhou, Nan
The information collected regarding group activity in a collaborative learning environment requires classifying, structuring and processing. The aim is to process this information in order to extract, reveal and provide students and tutors with valuable knowledge, awareness and feedback in order to successfully perform the collaborative learning activity. However, the large amount of information generated during online group activity may be timeconsuming to process and, hence, can hinder the realtime delivery of the information. In this study we show how a Gridbased paradigm can be used to effectively process and present the information regarding group activity gathered in the log files under a collaborative environment. The computational power of the Grid makes it possible to process a huge amount of event information, compute statistical results and present them, when needed, to the members of the online group and the tutors, who are geographically distributed.
Fri, 13 Apr 2018 11:33:25 GMT
http://hdl.handle.net/2117/116247
20180413T11:33:25Z
Xhafa Xhafa, Fatos
Caballé Llobet, Santiago
Daradoumis, Thanasis
Zhou, Nan
The information collected regarding group activity in a collaborative learning environment requires classifying, structuring and processing. The aim is to process this information in order to extract, reveal and provide students and tutors with valuable knowledge, awareness and feedback in order to successfully perform the collaborative learning activity. However, the large amount of information generated during online group activity may be timeconsuming to process and, hence, can hinder the realtime delivery of the information. In this study we show how a Gridbased paradigm can be used to effectively process and present the information regarding group activity gathered in the log files under a collaborative environment. The computational power of the Grid makes it possible to process a huge amount of event information, compute statistical results and present them, when needed, to the members of the online group and the tutors, who are geographically distributed.

Underthecell routing to improve manufacturability
http://hdl.handle.net/2117/115584
Underthecell routing to improve manufacturability
Vidal Obiols, Alexandre; Cortadella Fortuny, Jordi; Petit Silvestre, Jordi
The progressive miniaturization of technology and the unequal scalability of the BEOL and FEOL layers aggravate the routing congestion problem and have a negative impact on manufacturability. Standard cells are designed in a way that they can be treated as black boxes during physical design. However, this abstraction often prevents an efficient use of its internal free resources.
This paper proposes an effective approach for using internal routing resources without sacrificing modularity. By using cell generation tools for regular layouts, libraries are enriched with cell instances that have lateral pins and allow underthecell connections between adjacent cells, thus reducing pin count, via count and routing congestion.
An approach to generate cells with regular layouts and lateral pins is proposed. Additionally, algorithms to maximize the impact of underthecell routing are presented. The proposed techniques are integrated in an industrial design flow. Experimental results show a significant reduction of design rule check violations with negligible impact on timing.
Thu, 22 Mar 2018 14:26:47 GMT
http://hdl.handle.net/2117/115584
20180322T14:26:47Z
Vidal Obiols, Alexandre
Cortadella Fortuny, Jordi
Petit Silvestre, Jordi
The progressive miniaturization of technology and the unequal scalability of the BEOL and FEOL layers aggravate the routing congestion problem and have a negative impact on manufacturability. Standard cells are designed in a way that they can be treated as black boxes during physical design. However, this abstraction often prevents an efficient use of its internal free resources.
This paper proposes an effective approach for using internal routing resources without sacrificing modularity. By using cell generation tools for regular layouts, libraries are enriched with cell instances that have lateral pins and allow underthecell connections between adjacent cells, thus reducing pin count, via count and routing congestion.
An approach to generate cells with regular layouts and lateral pins is proposed. Additionally, algorithms to maximize the impact of underthecell routing are presented. The proposed techniques are integrated in an industrial design flow. Experimental results show a significant reduction of design rule check violations with negligible impact on timing.

Synthesis of alldigital delay lines
http://hdl.handle.net/2117/115402
Synthesis of alldigital delay lines
Moreno Vega, Alberto; Cortadella Fortuny, Jordi
The synthesis of delay lines (DLs) is a core task during the generation of matched delays, ring oscillator clocks or delay monitors. The main figure of merit of a DL is the fidelity to track variability. Unfortunately, complex systems have a great diversity of timing paths that exhibit different sensitivities to static and dynamic variations. Designing DLs that capture this diversity is an ardous task. This paper proposes an algorithmic approach for the synthesis of DLs that can be integrated in a conventional design flow. The algorithm uses heuristics to perform a combinatorial search in a vast space of solutions that combine different types of gates and wire lengths. The synthesized DLs are (1) all digital, i.e., built of conventional standard cells, (2) accurate in tracking variability and (3) configurable at runtime. Experimental results with a commercial standard cell library confirm the quality of the DLs that only exhibit delay mismatches of about 1% on average over all PVT corners.
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Mon, 19 Mar 2018 12:51:27 GMT
http://hdl.handle.net/2117/115402
20180319T12:51:27Z
Moreno Vega, Alberto
Cortadella Fortuny, Jordi
The synthesis of delay lines (DLs) is a core task during the generation of matched delays, ring oscillator clocks or delay monitors. The main figure of merit of a DL is the fidelity to track variability. Unfortunately, complex systems have a great diversity of timing paths that exhibit different sensitivities to static and dynamic variations. Designing DLs that capture this diversity is an ardous task. This paper proposes an algorithmic approach for the synthesis of DLs that can be integrated in a conventional design flow. The algorithm uses heuristics to perform a combinatorial search in a vast space of solutions that combine different types of gates and wire lengths. The synthesized DLs are (1) all digital, i.e., built of conventional standard cells, (2) accurate in tracking variability and (3) configurable at runtime. Experimental results with a commercial standard cell library confirm the quality of the DLs that only exhibit delay mismatches of about 1% on average over all PVT corners.

The parallel approximability of a subclass of quadratic programming
http://hdl.handle.net/2117/115216
The parallel approximability of a subclass of quadratic programming
Serna Iglesias, María José; Xhafa Xhafa, Fatos
In this paper we deal with the parallel approximability of a special class of Quadratic Programming (QP), called Smooth Positive Quadratic Programming. This subclass of QP is obtained by imposing restrictions on the coefficients of the QP instance. The Smoothness condition restricts the magnitudes of the coefficients while the positiveness requires that all the coefficients be nonnegative. Interestingly, even with these restrictions several combinatorial problems can be modeled by Smooth QP. We show NC Approximation Schemes for the instances of Smooth Positive QP. This is done by reducing the instance of QP to an instance of Positive Linear Programming, finding in NC an approximate fractional solution to the obtained program, and then rounding the fractional solution to an integer approximate solution for the original problem. Then we show how to extend the result for positive instances of bounded degree to Smooth Integer Programming problems. Finally, we formulate several important combinatorial problems as Positive Quadratic Programs (or Positive Integer Programs) in packing/covering form and show that the techniques presented can be used to obtain NC Approximation Schemes for "dense" instances of such problems.
Thu, 15 Mar 2018 13:50:18 GMT
http://hdl.handle.net/2117/115216
20180315T13:50:18Z
Serna Iglesias, María José
Xhafa Xhafa, Fatos
In this paper we deal with the parallel approximability of a special class of Quadratic Programming (QP), called Smooth Positive Quadratic Programming. This subclass of QP is obtained by imposing restrictions on the coefficients of the QP instance. The Smoothness condition restricts the magnitudes of the coefficients while the positiveness requires that all the coefficients be nonnegative. Interestingly, even with these restrictions several combinatorial problems can be modeled by Smooth QP. We show NC Approximation Schemes for the instances of Smooth Positive QP. This is done by reducing the instance of QP to an instance of Positive Linear Programming, finding in NC an approximate fractional solution to the obtained program, and then rounding the fractional solution to an integer approximate solution for the original problem. Then we show how to extend the result for positive instances of bounded degree to Smooth Integer Programming problems. Finally, we formulate several important combinatorial problems as Positive Quadratic Programs (or Positive Integer Programs) in packing/covering form and show that the techniques presented can be used to obtain NC Approximation Schemes for "dense" instances of such problems.

Parallel skeletons for Tabu search method
http://hdl.handle.net/2117/115214
Parallel skeletons for Tabu search method
Blesa Aguilera, Maria Josep; Hernàndez, Lluis; Xhafa Xhafa, Fatos
We present two generic parallel skeletons for the tabu search methoda well known metaheuristic for approximately solving combinatorial optimization problems. The first skeleton is based on independent runs while the second in the classical masterslave model. Our starting point is the design and implementation of a sequential skeleton that is used later as basis for the two parallel skeletons. Both skeletons provide the user with the following: a permit to obtain parallel implementations of the tabu search method for concrete combinatorial optimization problems from existing sequential implementations; there is no need for the user to know either parallel programming or communication libraries; and the parallel implementation of tabu search for a concrete problem is obtained automatically from a sequential implementation of tabu search for the problem. The skeletons, however, require from the user a sequential instantiation of the tabu search method for the problem at hand. The skeletons are implemented in C++ using MPI as the communication library and offer genericity, flexibility, component reuse, robustness and time savings. We have instantiated the two skeletons for the 01 multidimensional knapsack problem, among others, for which we report computational results.
Thu, 15 Mar 2018 13:33:27 GMT
http://hdl.handle.net/2117/115214
20180315T13:33:27Z
Blesa Aguilera, Maria Josep
Hernàndez, Lluis
Xhafa Xhafa, Fatos
We present two generic parallel skeletons for the tabu search methoda well known metaheuristic for approximately solving combinatorial optimization problems. The first skeleton is based on independent runs while the second in the classical masterslave model. Our starting point is the design and implementation of a sequential skeleton that is used later as basis for the two parallel skeletons. Both skeletons provide the user with the following: a permit to obtain parallel implementations of the tabu search method for concrete combinatorial optimization problems from existing sequential implementations; there is no need for the user to know either parallel programming or communication libraries; and the parallel implementation of tabu search for a concrete problem is obtained automatically from a sequential implementation of tabu search for the problem. The skeletons, however, require from the user a sequential instantiation of the tabu search method for the problem at hand. The skeletons are implemented in C++ using MPI as the communication library and offer genericity, flexibility, component reuse, robustness and time savings. We have instantiated the two skeletons for the 01 multidimensional knapsack problem, among others, for which we report computational results.

Increasing the robustness of digital circuits with ring oscillator clocks
http://hdl.handle.net/2117/114922
Increasing the robustness of digital circuits with ring oscillator clocks
Machado, Lucas; Roca Pérez, Antoni; Cortadella Fortuny, Jordi
Technology scaling enables lower supply voltages, but also increases power density of integrated circuits. In this context, power integrity becomes a major concern in the implementation of highperformance designs. This paper analyzes the influence of Ring Oscillator Clocks (ROCs) on mitigating the impacts of voltage noise. A design with an ROC as the clock source is able to work correctly even in the presence of severe and unpredictable voltage emergencies, without degrading the average performance and power metrics of the circuit. ROCs offer an instantaneous and continuous adaptation to the environment conditions, thus reducing the margins used to prevent timing failures. ROCs provide robustness independently of the power delivery network, thus relaxing
the constraints required for the design of the PCB and package. As a byproduct, the inherent jitter generated by ROCs produces a spreadspectrum effect that reduces electromagnetic emissions.
Thu, 08 Mar 2018 11:16:26 GMT
http://hdl.handle.net/2117/114922
20180308T11:16:26Z
Machado, Lucas
Roca Pérez, Antoni
Cortadella Fortuny, Jordi
Technology scaling enables lower supply voltages, but also increases power density of integrated circuits. In this context, power integrity becomes a major concern in the implementation of highperformance designs. This paper analyzes the influence of Ring Oscillator Clocks (ROCs) on mitigating the impacts of voltage noise. A design with an ROC as the clock source is able to work correctly even in the presence of severe and unpredictable voltage emergencies, without degrading the average performance and power metrics of the circuit. ROCs offer an instantaneous and continuous adaptation to the environment conditions, thus reducing the margins used to prevent timing failures. ROCs provide robustness independently of the power delivery network, thus relaxing
the constraints required for the design of the PCB and package. As a byproduct, the inherent jitter generated by ROCs produces a spreadspectrum effect that reduces electromagnetic emissions.

Waveform Transition Graphs: a designerfriendly formalism for asynchronous behaviours
http://hdl.handle.net/2117/114897
Waveform Transition Graphs: a designerfriendly formalism for asynchronous behaviours
Cortadella Fortuny, Jordi; Moreno Vega, Alberto; Sokolov, Danil; Yakovlev, Alex; Lloyd, David
The paper proposes a new formal model for describing asynchronous behaviours involving the interplay of causality, concurrency and choice. The model is called Waveform Transition Graphs. Its main aim is simplifying the learning process for industrial engineers in accessing powerful synthesis tools provided for Signal Transition Graphs by sacrificing some of the expressive power of the latter. This formalism is developed based on feedback from engineers of Dialog Semiconductor.
Wed, 07 Mar 2018 12:36:21 GMT
http://hdl.handle.net/2117/114897
20180307T12:36:21Z
Cortadella Fortuny, Jordi
Moreno Vega, Alberto
Sokolov, Danil
Yakovlev, Alex
Lloyd, David
The paper proposes a new formal model for describing asynchronous behaviours involving the interplay of causality, concurrency and choice. The model is called Waveform Transition Graphs. Its main aim is simplifying the learning process for industrial engineers in accessing powerful synthesis tools provided for Signal Transition Graphs by sacrificing some of the expressive power of the latter. This formalism is developed based on feedback from engineers of Dialog Semiconductor.

Boolean decomposition for AIG optimization
http://hdl.handle.net/2117/114892
Boolean decomposition for AIG optimization
Machado, Lucas; Cortadella Fortuny, Jordi
Restructuring techniques for AndInverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the original AIG structure and limited by single output optimizations. This paper investigates AIG optimization for area, exploring how far Boolean methods can reduce AIG nodes through local optimization.Boolean division is applied for multioutput functions using twoliteral divisors and Boolean decomposition is introduced as a method for AIG optimization. Multioutput blocks are extracted from the AIG and optimized, achieving a further AIG node reduction of 7.76% on average for ITC99 and MCNC benchmarks.
Wed, 07 Mar 2018 10:40:48 GMT
http://hdl.handle.net/2117/114892
20180307T10:40:48Z
Machado, Lucas
Cortadella Fortuny, Jordi
Restructuring techniques for AndInverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the original AIG structure and limited by single output optimizations. This paper investigates AIG optimization for area, exploring how far Boolean methods can reduce AIG nodes through local optimization.Boolean division is applied for multioutput functions using twoliteral divisors and Boolean decomposition is introduced as a method for AIG optimization. Multioutput blocks are extracted from the AIG and optimized, achieving a further AIG node reduction of 7.76% on average for ITC99 and MCNC benchmarks.