QINE - Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades
http://hdl.handle.net/2117/3644
2024-03-28T09:15:53ZEnhanced DC-Link Capacitor Voltage Balancing Control of DC-AC Multilevel Multileg Converters
http://hdl.handle.net/2117/28072
Enhanced DC-Link Capacitor Voltage Balancing Control of DC-AC Multilevel Multileg Converters
Busquets Monge, Sergio; Maheshwari, RamKrishan; Nicolás Apruzzese, Joan; Lupón Roses, Emilio; Munk Nielsen, Stig; Bordonau Farrerons, José
This paper presents a capacitor voltage balancing control applicable to any multilevel dc-ac converter formed by a single set of series-connected capacitors implementing the dc link and semiconductor devices, such as the diode-clamped topology. The control is defined for any number of dc-link voltage levels and converter legs (for single-phase and multiphase systems), guaranteeing the capacitor voltage control for any modulation index value and load (from idle mode to full power). The associated control loop small-signal transfer function is presented, from which optimum compensator design guidelines are derived. The improvement in control performance is verified through simulation and experiments comparing with a previous balancing control strategy in a four-level three-phase dc-ac conversion system. The satisfactory control performance is also verified through simulation in a four-level five-phase dc-ac conversion system.
2015-05-27T15:54:29ZBusquets Monge, SergioMaheshwari, RamKrishanNicolás Apruzzese, JoanLupón Roses, EmilioMunk Nielsen, StigBordonau Farrerons, JoséThis paper presents a capacitor voltage balancing control applicable to any multilevel dc-ac converter formed by a single set of series-connected capacitors implementing the dc link and semiconductor devices, such as the diode-clamped topology. The control is defined for any number of dc-link voltage levels and converter legs (for single-phase and multiphase systems), guaranteeing the capacitor voltage control for any modulation index value and load (from idle mode to full power). The associated control loop small-signal transfer function is presented, from which optimum compensator design guidelines are derived. The improvement in control performance is verified through simulation and experiments comparing with a previous balancing control strategy in a four-level three-phase dc-ac conversion system. The satisfactory control performance is also verified through simulation in a four-level five-phase dc-ac conversion system.Improving security in cache memory by power efficient scrambling technique
http://hdl.handle.net/2117/28039
Improving security in cache memory by power efficient scrambling technique
Neagu, Madalin; Miclea, Liviu; Manich Bou, Salvador
The last decade has recorded an increase in security protocols for integrated circuits and memory systems, because of device specific attacks such as side-channel monitoring and cold boot and also because sensitive information is stored in such devices. The scope of this study is to propose new security measures which can be applied in memory systems, in order to make the stored data unusable, if retrieved successfully by any type of attack. The security technique uses interleaved scrambling vectors to scramble the data retained in a memory system and employs several dissemination rules. The proposed technique is investigated and assessed from several perspectives, such as power consumption, time performance and area overhead.
2015-05-25T17:05:40ZNeagu, MadalinMiclea, LiviuManich Bou, SalvadorThe last decade has recorded an increase in security protocols for integrated circuits and memory systems, because of device specific attacks such as side-channel monitoring and cold boot and also because sensitive information is stored in such devices. The scope of this study is to propose new security measures which can be applied in memory systems, in order to make the stored data unusable, if retrieved successfully by any type of attack. The security technique uses interleaved scrambling vectors to scramble the data retained in a memory system and employs several dissemination rules. The proposed technique is investigated and assessed from several perspectives, such as power consumption, time performance and area overhead.Reliability estimation at block-level granularity of spin-transfer-torque MRAMs
http://hdl.handle.net/2117/27040
Reliability estimation at block-level granularity of spin-transfer-torque MRAMs
Di Carlo, Stefano; Indaco, Marco; Prinetto, Paolo; Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan
In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability and aging phenomena, making reliability prediction a growing concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve the desired reliability target for the memory under study.
2015-03-26T09:25:11ZDi Carlo, StefanoIndaco, MarcoPrinetto, PaoloVatajelu, Elena IoanaRodríguez Montañés, RosaFigueras Pàmies, JoanIn recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability and aging phenomena, making reliability prediction a growing concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve the desired reliability target for the memory under study.A Method for Detecting Resistive Opens in Buses
http://hdl.handle.net/2117/26847
A Method for Detecting Resistive Opens in Buses
Rius Vázquez, José
The method is based on the modification of bus connectivity to force bus oscillation during testing. The oscillation frequency depends on the open resistance and location on the line. Comparison of the frequency with a reference allows the detection and eventual location of the defect. Electrical
simulations and preliminary experiments on a test chip show the detection capabilities and the feasibility of the proposed method.
2015-03-19T13:15:07ZRius Vázquez, JoséThe method is based on the modification of bus connectivity to force bus oscillation during testing. The oscillation frequency depends on the open resistance and location on the line. Comparison of the frequency with a reference allows the detection and eventual location of the defect. Electrical
simulations and preliminary experiments on a test chip show the detection capabilities and the feasibility of the proposed method.On the use of error detecting and correcting codes to boost security in caches against side channel attacks
http://hdl.handle.net/2117/26828
On the use of error detecting and correcting codes to boost security in caches against side channel attacks
Neagu, Madalin; Miclea, Liviu; Manich Bou, Salvador
Microprocessor memory is sensitive to cold boot attacks. In this kind of attacks, memory remanence is exploited to download its content after the microprocessor has been struck by a hard boot. If just in this moment, a crypto-algorithm was in execution, the memory data can be downloaded into a backup memory and specialized tools can be used to extract the secret keys.
In the main memory data can be protected using efficient encryption techniques but in caches this is not possible unless the performance becomes seriously degraded. Recently, an interleaved scrambling technique (IST) was presented to improve
the security of caches against cold boot attacks. While IST is effective for this particular kind of attacks, a weakness exists
against side channel attacks, in particular using power analysis.
Reliability of data in caches is warranted by means of error detecting and correcting codes. In this work it is shown how these
kinds of codes can be used not only to improve reliability but also the security of data. In particular, a self-healing technique is
selected to make the IST technique robust against side channel attacks using power analysis.
2015-03-19T10:48:23ZNeagu, MadalinMiclea, LiviuManich Bou, SalvadorMicroprocessor memory is sensitive to cold boot attacks. In this kind of attacks, memory remanence is exploited to download its content after the microprocessor has been struck by a hard boot. If just in this moment, a crypto-algorithm was in execution, the memory data can be downloaded into a backup memory and specialized tools can be used to extract the secret keys.
In the main memory data can be protected using efficient encryption techniques but in caches this is not possible unless the performance becomes seriously degraded. Recently, an interleaved scrambling technique (IST) was presented to improve
the security of caches against cold boot attacks. While IST is effective for this particular kind of attacks, a weakness exists
against side channel attacks, in particular using power analysis.
Reliability of data in caches is warranted by means of error detecting and correcting codes. In this work it is shown how these
kinds of codes can be used not only to improve reliability but also the security of data. In particular, a self-healing technique is
selected to make the IST technique robust against side channel attacks using power analysis.Design and implementation of automatic test equipment IP module
http://hdl.handle.net/2117/26780
Design and implementation of automatic test equipment IP module
Fransi Palos, Sergi; Farre Lozano, Goretti; Garcia Deiros, Lucas; Manich Bou, Salvador
This paper presents an Intellectual Property (IP) module that includes fully functional autonomous Automatic Test Equipment (ATE). The module analyses responses from the Device Under Test (DUT) after sending test vectors to the device. Communication with the DUT is maintained through a synchronous bidirectional serial channel. The module has been designed for a fail-safe level of security, which means any single fault producing an erroneous output is detected. Several IP-ATEs can be synthesized in a single hardware platform to operate independently or coordinately.
2015-03-18T08:50:30ZFransi Palos, SergiFarre Lozano, GorettiGarcia Deiros, LucasManich Bou, SalvadorThis paper presents an Intellectual Property (IP) module that includes fully functional autonomous Automatic Test Equipment (ATE). The module analyses responses from the Device Under Test (DUT) after sending test vectors to the device. Communication with the DUT is maintained through a synchronous bidirectional serial channel. The module has been designed for a fail-safe level of security, which means any single fault producing an erroneous output is detected. Several IP-ATEs can be synthesized in a single hardware platform to operate independently or coordinately.La Promoció 108 compleix 50 anys (1964-2014): història, entorn i records
http://hdl.handle.net/2117/26543
La Promoció 108 compleix 50 anys (1964-2014): història, entorn i records
del Cerro, Jordi; Cusí Cusí, Carles; Figueras Pàmies, Joan
2015-02-27T13:40:37Zdel Cerro, JordiCusí Cusí, CarlesFigueras Pàmies, JoanDefeating microprobing attacks using a resource efficient detection circuit
http://hdl.handle.net/2117/26536
Defeating microprobing attacks using a resource efficient detection circuit
Weiner, Michael; Manich Bou, Salvador; Sigl, Georg
Microprobing is an attack technique against integrated circuits implementing security functions, such as OTP tokens or smartcards. It allows intercepting secrets from onchip wires as well as injecting faults for other attacks. While the necessity to etch open chip packages and to remove the passivation layer makes microprobing appear expensive, it was shown that a successful attack can be run with equipment worth a few thousand euros. On the protector’s side, however, appropriate countermeasures such as active shields, redundancy of core components, or analog detection circuits containing large capacitors, are still expensive. We present a resource efficient microbing detection circuit that we call Low Area Probing Detector (LAPD). It measures minimal timing differences between on-chip wires caused by the capacitive load of microprobes. Simulations show that it can detect up-todate probes with capacitances as low as 10 fF. As a novelty, the LAPD is merely based on digital components and does not require analog circuitry, which reduces the required area and process steps compared to previous approaches.
2015-02-27T10:43:24ZWeiner, MichaelManich Bou, SalvadorSigl, GeorgMicroprobing is an attack technique against integrated circuits implementing security functions, such as OTP tokens or smartcards. It allows intercepting secrets from onchip wires as well as injecting faults for other attacks. While the necessity to etch open chip packages and to remove the passivation layer makes microprobing appear expensive, it was shown that a successful attack can be run with equipment worth a few thousand euros. On the protector’s side, however, appropriate countermeasures such as active shields, redundancy of core components, or analog detection circuits containing large capacitors, are still expensive. We present a resource efficient microbing detection circuit that we call Low Area Probing Detector (LAPD). It measures minimal timing differences between on-chip wires caused by the capacitive load of microprobes. Simulations show that it can detect up-todate probes with capacitances as low as 10 fF. As a novelty, the LAPD is merely based on digital components and does not require analog circuitry, which reduces the required area and process steps compared to previous approaches.Criteria for indirect measurements in M-S testing
http://hdl.handle.net/2117/26217
Criteria for indirect measurements in M-S testing
Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan
Analog and mixed-signal circuit testing is a cballenging
task demanding large amounts of resources. In order to battle
against this drawback, alternate testing has been established as an
eflicient way of testing analog and M-S circuits by using indirect
measures instead of the classic specification based testing. In
this work we propose the use of Kendall's Tau rank correlation
coeflicient for rating the suitability of a set of candidate indirect
measures to be used in mixed-signal testing. Such criterion is
shown to be adequate since it allows to avoid or minimize
information redundancy in the measures set. As a proof of
concept, a 4th order band-pass Butterworth filter has been
simulated under the presence of process variations. The circuit
has been tested using a subset of measures selected according to
minimum Kendall's Tau coeflicient. Analog test efliciency metrics
are reported showing test misclassification rate is among the best
15% possible, therefore validating the proposal.
2015-02-04T14:53:54ZGómez Pau, ÁlvaroBalado Suárez, Luz MaríaFigueras Pàmies, JoanAnalog and mixed-signal circuit testing is a cballenging
task demanding large amounts of resources. In order to battle
against this drawback, alternate testing has been established as an
eflicient way of testing analog and M-S circuits by using indirect
measures instead of the classic specification based testing. In
this work we propose the use of Kendall's Tau rank correlation
coeflicient for rating the suitability of a set of candidate indirect
measures to be used in mixed-signal testing. Such criterion is
shown to be adequate since it allows to avoid or minimize
information redundancy in the measures set. As a proof of
concept, a 4th order band-pass Butterworth filter has been
simulated under the presence of process variations. The circuit
has been tested using a subset of measures selected according to
minimum Kendall's Tau coeflicient. Analog test efliciency metrics
are reported showing test misclassification rate is among the best
15% possible, therefore validating the proposal.Real-time transient error and induced noise cancellation in linear analog filters using learning-assisted adaptive analog checksums
http://hdl.handle.net/2117/25784
Real-time transient error and induced noise cancellation in linear analog filters using learning-assisted adaptive analog checksums
Gómez Pau, Álvaro; Banerjee, Suvadeep; Chatterjee, Abhijit
Analog circuits are sensitive to signal aggressions and power supply noise, crosstalk coupling and alpha particle strikes can cause significant degradation of circuit's SNR. This research proposes a novel approach to real-time transient error and induced noise cancellation in linear analog circuits using analog checksums. It is based on the use of state space representations of analog filters and is a significant advancement over prior research that addressed only hard parametric deviations. A key innovation is the use of less than minimum distance checksum codes for error detection and correction using real-time learning of the likely source of transient errors and noise within the analog circuit. By running a simple hardware-directed search algorithm, the circuit 'learns' how best to compensate for the injected signal disturbances with low overhead under the assumption that the source of the injected errors/noise and the error/noise statistics are stationary over time. Successful simulations and preliminary experimental results demonstrate almost complete compensation of injected noise, therefore validating the proposal.
2015-01-15T18:59:38ZGómez Pau, ÁlvaroBanerjee, SuvadeepChatterjee, AbhijitAnalog circuits are sensitive to signal aggressions and power supply noise, crosstalk coupling and alpha particle strikes can cause significant degradation of circuit's SNR. This research proposes a novel approach to real-time transient error and induced noise cancellation in linear analog circuits using analog checksums. It is based on the use of state space representations of analog filters and is a significant advancement over prior research that addressed only hard parametric deviations. A key innovation is the use of less than minimum distance checksum codes for error detection and correction using real-time learning of the likely source of transient errors and noise within the analog circuit. By running a simple hardware-directed search algorithm, the circuit 'learns' how best to compensate for the injected signal disturbances with low overhead under the assumption that the source of the injected errors/noise and the error/noise statistics are stationary over time. Successful simulations and preliminary experimental results demonstrate almost complete compensation of injected noise, therefore validating the proposal.