Articles de revista
http://hdl.handle.net/2117/79838
2024-03-29T01:34:01Z
2024-03-29T01:34:01Z
Quiescent current analysis and experimentation of defective CMOS circuits
Segura, J A
Champac, V H
Rodríguez Montañés, Rosa
Figueras Pàmies, Joan
Rubio Sola, Jose Antonio
http://hdl.handle.net/2117/402335
2024-02-26T00:27:46Z
2024-02-21T07:14:06Z
Quiescent current analysis and experimentation of defective CMOS circuits
Segura, J A; Champac, V H; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Rubio Sola, Jose Antonio
Physical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on I DDQ has been investigated by electrical simulation and experimentation.
2024-02-21T07:14:06Z
Segura, J A
Champac, V H
Rodríguez Montañés, Rosa
Figueras Pàmies, Joan
Rubio Sola, Jose Antonio
Physical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on I DDQ has been investigated by electrical simulation and experimentation.
Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact
Calomarde Palomino, Antonio
Manich Bou, Salvador
Rubio Sola, Jose Antonio
Gamiz, Francisco
http://hdl.handle.net/2117/367782
2022-05-29T14:58:47Z
2022-05-27T10:30:56Z
Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact
Calomarde Palomino, Antonio; Manich Bou, Salvador; Rubio Sola, Jose Antonio; Gamiz, Francisco
This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 3D TCAD simulations have been performed to obtain a detailed map of the sensitivity areas in a full cell 6-T SRAM 22 nm bulk-FinFET process. The influence of the well depth on the charge collected by the drain devices of the SRAM cell has been studied, and it has been concluded that the collected charge can be reduced down to 300% simply by modifying the depth of the well, without affecting the performance of the cell. Different PTS layer depths have been analyzed in order to calculate which value minimizes the impact of the charge generated by an ion during its track along the FinFET body. The simulations carried out allow to conclude that the incorporation of a PTS layer not only reduces the leakage current, but also reduces the amount of charge, delivered by the ion, that reaches the drain region. Simulation results also show that the fraction of the charge generated by the ion impact, which is collected by the drain, mainly depends on the depth of the wells, whereas the PTS layer hardly modifies the collected charge.
2022-05-27T10:30:56Z
Calomarde Palomino, Antonio
Manich Bou, Salvador
Rubio Sola, Jose Antonio
Gamiz, Francisco
This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 3D TCAD simulations have been performed to obtain a detailed map of the sensitivity areas in a full cell 6-T SRAM 22 nm bulk-FinFET process. The influence of the well depth on the charge collected by the drain devices of the SRAM cell has been studied, and it has been concluded that the collected charge can be reduced down to 300% simply by modifying the depth of the well, without affecting the performance of the cell. Different PTS layer depths have been analyzed in order to calculate which value minimizes the impact of the charge generated by an ion during its track along the FinFET body. The simulations carried out allow to conclude that the incorporation of a PTS layer not only reduces the leakage current, but also reduces the amount of charge, delivered by the ion, that reaches the drain region. Simulation results also show that the fraction of the charge generated by the ion impact, which is collected by the drain, mainly depends on the depth of the wells, whereas the PTS layer hardly modifies the collected charge.
On-line remaining useful life estimation of power connectors focused on predictive maintenance
Riba Ruiz, Jordi-Roger
Gómez Pau, Álvaro
Martínez Reyes, Jimmy Arturo
Moreno Eguilaz, Juan Manuel
http://hdl.handle.net/2117/357335
2022-07-31T03:37:21Z
2021-11-30T14:05:13Z
On-line remaining useful life estimation of power connectors focused on predictive maintenance
Riba Ruiz, Jordi-Roger; Gómez Pau, Álvaro; Martínez Reyes, Jimmy Arturo; Moreno Eguilaz, Juan Manuel
Connections are critical elements in power systems, exhibiting higher failure probability. Power connectors are considered secondary simple devices in power systems despite their key role, since a failure in one such element can lead to major issues. Thus, it is of vital interest to develop predictive maintenance approaches to minimize these issues. This paper proposes an on-line method to determine the remaining useful life (RUL) of power connectors. It is based on a simple and accurate model of the degradation with time of the electrical resistance of the connector, which only has two parameters, whose values are identified from on-line acquired data (voltage drop across the connector, electric current and temperature). The accuracy of the model presented in this paper is compared with the widely applied autoregressive integrated moving average model (ARIMA), showing enhanced performance. Next, a criterion to determine the RUL is proposed, which is based on the inflection point of the expression describing the electrical resistance degradation. This strategy allows determination of when the connector must be replaced, thus easing predictive maintenance tasks. Experimental results from seven connectors show the potential and viability of the suggested method, which can be applied to many other devices.
2021-11-30T14:05:13Z
Riba Ruiz, Jordi-Roger
Gómez Pau, Álvaro
Martínez Reyes, Jimmy Arturo
Moreno Eguilaz, Juan Manuel
Connections are critical elements in power systems, exhibiting higher failure probability. Power connectors are considered secondary simple devices in power systems despite their key role, since a failure in one such element can lead to major issues. Thus, it is of vital interest to develop predictive maintenance approaches to minimize these issues. This paper proposes an on-line method to determine the remaining useful life (RUL) of power connectors. It is based on a simple and accurate model of the degradation with time of the electrical resistance of the connector, which only has two parameters, whose values are identified from on-line acquired data (voltage drop across the connector, electric current and temperature). The accuracy of the model presented in this paper is compared with the widely applied autoregressive integrated moving average model (ARIMA), showing enhanced performance. Next, a criterion to determine the RUL is proposed, which is based on the inflection point of the expression describing the electrical resistance degradation. This strategy allows determination of when the connector must be replaced, thus easing predictive maintenance tasks. Experimental results from seven connectors show the potential and viability of the suggested method, which can be applied to many other devices.
RRAM random number generator based on train of pulses
Yang, Binbin
Arumi Delgado, Daniel
Manich Bou, Salvador
Gómez Pau, Álvaro
Rodríguez Montañés, Rosa
Bargalló González, Mireia
Campabadal, Francesca
Fang, Liang
http://hdl.handle.net/2117/355114
2023-08-13T02:03:01Z
2021-11-02T09:42:54Z
RRAM random number generator based on train of pulses
Yang, Binbin; Arumi Delgado, Daniel; Manich Bou, Salvador; Gómez Pau, Álvaro; Rodríguez Montañés, Rosa; Bargalló González, Mireia; Campabadal, Francesca; Fang, Liang
In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications.
2021-11-02T09:42:54Z
Yang, Binbin
Arumi Delgado, Daniel
Manich Bou, Salvador
Gómez Pau, Álvaro
Rodríguez Montañés, Rosa
Bargalló González, Mireia
Campabadal, Francesca
Fang, Liang
In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications.
Serial RRAM cell for secure bit concealing
Yang, Binbin
Arumi Delgado, Daniel
Manich Bou, Salvador
Gómez Pau, Álvaro
Rodríguez Montañés, Rosa
Bargalló González, Mireia
Campabadal, Francesca
Fang, Liang
http://hdl.handle.net/2117/355112
2023-08-13T00:52:13Z
2021-11-02T09:35:14Z
Serial RRAM cell for secure bit concealing
Yang, Binbin; Arumi Delgado, Daniel; Manich Bou, Salvador; Gómez Pau, Álvaro; Rodríguez Montañés, Rosa; Bargalló González, Mireia; Campabadal, Francesca; Fang, Liang
Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal.
2021-11-02T09:35:14Z
Yang, Binbin
Arumi Delgado, Daniel
Manich Bou, Salvador
Gómez Pau, Álvaro
Rodríguez Montañés, Rosa
Bargalló González, Mireia
Campabadal, Francesca
Fang, Liang
Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal.
Enhanced serial RRAM cell for unpredictable bit generation
Rodríguez Montañés, Rosa
Arumi Delgado, Daniel
Gómez-Pau, Álvaro
Manich Bou, Salvador
Bargalló González, Mireia
Campabadal, Francesca
http://hdl.handle.net/2117/352375
2021-10-03T21:28:47Z
2021-09-28T10:33:02Z
Enhanced serial RRAM cell for unpredictable bit generation
Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Gómez-Pau, Álvaro; Manich Bou, Salvador; Bargalló González, Mireia; Campabadal, Francesca
In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpredictable bit. The basis of the operation considers starting from the Low Resistive State (LRS) in both devices (initialization step), then, one of them is switched to the High Resistive State (HRS) (bit generation step) without knowing, in advance, which one is the switching device (unmasking step). In this proposal, the larger resistance variability of HRS compared to LRS is considered to improve the masking performance of the cell (masking step). The presented experimental results are a proof-of-concept of the applicability of the proposal.
2021-09-28T10:33:02Z
Rodríguez Montañés, Rosa
Arumi Delgado, Daniel
Gómez-Pau, Álvaro
Manich Bou, Salvador
Bargalló González, Mireia
Campabadal, Francesca
In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpredictable bit. The basis of the operation considers starting from the Low Resistive State (LRS) in both devices (initialization step), then, one of them is switched to the High Resistive State (HRS) (bit generation step) without knowing, in advance, which one is the switching device (unmasking step). In this proposal, the larger resistance variability of HRS compared to LRS is considered to improve the masking performance of the cell (masking step). The presented experimental results are a proof-of-concept of the applicability of the proposal.
Indirect and adaptive test of analogue circuits based on preselected steady-state response measures
Gómez Pau, Álvaro
Lupón Roses, Emilio
Balado Suárez, Luz María
Figueras, Joan
http://hdl.handle.net/2117/336891
2021-05-20T14:33:48Z
2021-02-04T11:31:31Z
Indirect and adaptive test of analogue circuits based on preselected steady-state response measures
Gómez Pau, Álvaro; Lupón Roses, Emilio; Balado Suárez, Luz María; Figueras, Joan
Alternate testing techniques have been progressively adopted as a promising solution due to their effectiveness against classical specification-based test methods. This work presents a built-in test system, which adaptively generates an indirect digital signature characterising the circuit under test, which is later used to diagnose the actual performances relying on a statistical dictionary-based diagnosis method. The system is composed of an integrated digital signature generator and a digital control and acquisition subsystem. The signature generator is based on a converter architecture, in which the analogue range can be adapted to the magnitude of the indirect measure using the well known information of the fault-free circuit. The digital subsystem controls the proposed architecture and stores the digital codes sent by the integrated digital signature generator. The digital signature generator has been designed and fabricated in an industrial 65 nm complementary metal–oxide–semiconductor technology from STMicroelectronics, whereas the digital control and acquisition subsystem have been prototyped in a field-programmable gate array. The fabricated system has been used to test a biquad filter affected by parametric variations. Successful experimental results are reported showing the capabilities of the proposed adaptive test system to diagnose circuit performances with discrepancies as low as 1% of the actual real value.
2021-02-04T11:31:31Z
Gómez Pau, Álvaro
Lupón Roses, Emilio
Balado Suárez, Luz María
Figueras, Joan
Alternate testing techniques have been progressively adopted as a promising solution due to their effectiveness against classical specification-based test methods. This work presents a built-in test system, which adaptively generates an indirect digital signature characterising the circuit under test, which is later used to diagnose the actual performances relying on a statistical dictionary-based diagnosis method. The system is composed of an integrated digital signature generator and a digital control and acquisition subsystem. The signature generator is based on a converter architecture, in which the analogue range can be adapted to the magnitude of the indirect measure using the well known information of the fault-free circuit. The digital subsystem controls the proposed architecture and stores the digital codes sent by the integrated digital signature generator. The digital signature generator has been designed and fabricated in an industrial 65 nm complementary metal–oxide–semiconductor technology from STMicroelectronics, whereas the digital control and acquisition subsystem have been prototyped in a field-programmable gate array. The fabricated system has been used to test a biquad filter affected by parametric variations. Successful experimental results are reported showing the capabilities of the proposed adaptive test system to diagnose circuit performances with discrepancies as low as 1% of the actual real value.
A forming-free ReRAM cell with low operating voltage
Yang, Binbin
Xu, Nuo
Li, Cheng
Huang, Chenglong
Ma, Desheng
Liu, Jiahao
Arumi Delgado, Daniel
Fang, Liang
http://hdl.handle.net/2117/336279
2023-08-13T11:20:47Z
2021-02-01T12:38:56Z
A forming-free ReRAM cell with low operating voltage
Yang, Binbin; Xu, Nuo; Li, Cheng; Huang, Chenglong; Ma, Desheng; Liu, Jiahao; Arumi Delgado, Daniel; Fang, Liang
The unwanted electro-forming process is unavoidable for the practical application of most resistive random access memory (ReRAM) devices, which is always being one of the obstacles for the massive commercialization of this novel electronic device. In this letter, a forming-free Pt/Ti/(TiO2-x )/Ta2O5/Pt based ReRAM device is demonstrated with an additional feature of the low operation voltage. The fitting result of the measured I-V curves reveals that resistive switching of the fabricated device is conducted by the electrons trapping/de-trapping process in deep-level electron traps of the TiO2-x layer, which is formed through the spontaneous “oxygen grabbing” reaction in the interface of Ti and Ta2O5 during the film deposition. The plentiful oxygen vacancy defects and the thin resistive switching zone (TiO2-x ) ensure the forming-free and low operating voltage characteristics. Using “oxygen grabbing” to pre-produce abundant electron trapping centers for the resistive switching provides a simple way for the fabrication of the forming-free ReRAM device with low operating voltage, aiming to the high-density and low-power memory applications.
2021-02-01T12:38:56Z
Yang, Binbin
Xu, Nuo
Li, Cheng
Huang, Chenglong
Ma, Desheng
Liu, Jiahao
Arumi Delgado, Daniel
Fang, Liang
The unwanted electro-forming process is unavoidable for the practical application of most resistive random access memory (ReRAM) devices, which is always being one of the obstacles for the massive commercialization of this novel electronic device. In this letter, a forming-free Pt/Ti/(TiO2-x )/Ta2O5/Pt based ReRAM device is demonstrated with an additional feature of the low operation voltage. The fitting result of the measured I-V curves reveals that resistive switching of the fabricated device is conducted by the electrons trapping/de-trapping process in deep-level electron traps of the TiO2-x layer, which is formed through the spontaneous “oxygen grabbing” reaction in the interface of Ti and Ta2O5 during the film deposition. The plentiful oxygen vacancy defects and the thin resistive switching zone (TiO2-x ) ensure the forming-free and low operating voltage characteristics. Using “oxygen grabbing” to pre-produce abundant electron trapping centers for the resistive switching provides a simple way for the fabrication of the forming-free ReRAM device with low operating voltage, aiming to the high-density and low-power memory applications.
Sensor comparison for corona discharge detection under low pressure conditions
Riba Ruiz, Jordi-Roger
Gómez Pau, Álvaro
Moreno Eguilaz, Juan Manuel
http://hdl.handle.net/2117/330191
2022-05-17T11:04:38Z
2020-10-13T16:02:53Z
Sensor comparison for corona discharge detection under low pressure conditions
Riba Ruiz, Jordi-Roger; Gómez Pau, Álvaro; Moreno Eguilaz, Juan Manuel
Low pressure environments, situate insulation systems in a challenging position since partial discharges (PDs), corona and arc tracking are more likely to develop. Therefore, specific solutions are required to detect such harmful phenomena before major failure occurrence. This paper deals with three low-cost and small-size sensing methods, i.e., a single loop antenna, a visible-UV imaging sensor and the measurement of the leakage current to detect corona in the early stage, thus anticipating the appearance of severer effects such as arc tracking or disruptive breakdown. The three studied methods can be applied for an on-line monitoring of corona activity under low pressure environments, thus being compatible with predictive maintenance approaches. This on-line monitoring can be used to develop improved electrical protection devices able to detect such effects in an initial stage, thus improving current solutions which are unable to do so. All three studied sensors give consistent linear responses within the studied pressure range, i.e., 10-100 kPa, with almost no drift. The sensitivity of the visible-UV imaging sensor is slightly lower than that of the others, but it has the advantage of directly locating the discharge points. Results presented in this paper can be very useful for the more electrical aircraft (MEA), which is forcing electrical distribution systems to operate at higher voltage levels. Due to the little experience and scarcity of published data, the experimental results presented in this paper can be valuable for a better understanding of the combined action of high voltage and low pressure environments.
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2020-10-13T16:02:53Z
Riba Ruiz, Jordi-Roger
Gómez Pau, Álvaro
Moreno Eguilaz, Juan Manuel
Low pressure environments, situate insulation systems in a challenging position since partial discharges (PDs), corona and arc tracking are more likely to develop. Therefore, specific solutions are required to detect such harmful phenomena before major failure occurrence. This paper deals with three low-cost and small-size sensing methods, i.e., a single loop antenna, a visible-UV imaging sensor and the measurement of the leakage current to detect corona in the early stage, thus anticipating the appearance of severer effects such as arc tracking or disruptive breakdown. The three studied methods can be applied for an on-line monitoring of corona activity under low pressure environments, thus being compatible with predictive maintenance approaches. This on-line monitoring can be used to develop improved electrical protection devices able to detect such effects in an initial stage, thus improving current solutions which are unable to do so. All three studied sensors give consistent linear responses within the studied pressure range, i.e., 10-100 kPa, with almost no drift. The sensitivity of the visible-UV imaging sensor is slightly lower than that of the others, but it has the advantage of directly locating the discharge points. Results presented in this paper can be very useful for the more electrical aircraft (MEA), which is forcing electrical distribution systems to operate at higher voltage levels. Due to the little experience and scarcity of published data, the experimental results presented in this paper can be valuable for a better understanding of the combined action of high voltage and low pressure environments.
Uprating of transmission lines by means of HTLS conductors for a sustainable growth: challenges, opportunities, and research needs
Riba Ruiz, Jordi-Roger
Bogarra Rodríguez, Santiago
Gómez Pau, Álvaro
Moreno Eguilaz, Juan Manuel
http://hdl.handle.net/2117/328710
2022-12-01T01:31:55Z
2020-09-14T10:27:01Z
Uprating of transmission lines by means of HTLS conductors for a sustainable growth: challenges, opportunities, and research needs
Riba Ruiz, Jordi-Roger; Bogarra Rodríguez, Santiago; Gómez Pau, Álvaro; Moreno Eguilaz, Juan Manuel
This paper provides a comprehensive and critical review and evaluation of the technological state-of-the-art of high-temperature low-sag (HTLS) conductors by analyzing research articles, theses, reports, white papers and international standards. The growth of power demand requires new solutions to develop power transmission systems, while facing the issues related to power systems congestion. A possibility to solve the load growth issue is to increase the capacity of existing transmission systems by reconductoring the lines with new conductors, which are able to operate at higher temperatures, while limiting the sag and maintaining or reducing the required clearances, thus having more current carrying capacity than the existing ones. This paper also describes the limitations of such technology and identifies the research needs to fulfill the requirements of the industry and transmission system operators.
2020-09-14T10:27:01Z
Riba Ruiz, Jordi-Roger
Bogarra Rodríguez, Santiago
Gómez Pau, Álvaro
Moreno Eguilaz, Juan Manuel
This paper provides a comprehensive and critical review and evaluation of the technological state-of-the-art of high-temperature low-sag (HTLS) conductors by analyzing research articles, theses, reports, white papers and international standards. The growth of power demand requires new solutions to develop power transmission systems, while facing the issues related to power systems congestion. A possibility to solve the load growth issue is to increase the capacity of existing transmission systems by reconductoring the lines with new conductors, which are able to operate at higher temperatures, while limiting the sag and maintaining or reducing the required clearances, thus having more current carrying capacity than the existing ones. This paper also describes the limitations of such technology and identifies the research needs to fulfill the requirements of the industry and transmission system operators.