Enabling hardware randomization across the cache hierarchy in Linux-Class processors

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dc.contributor.authorDoblas, Max
dc.contributor.authorKostalampros, Ioannis-Vatistas
dc.contributor.authorMoretó Planas, Miquel
dc.contributor.authorHernández Luz, Carles
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2020-06-15T07:29:08Z
dc.date.available2020-06-15T07:29:08Z
dc.date.issued2020
dc.description.abstractThe most promising secure-cache design approaches use cache-set randomization to index cache contents thus thwarting cache side-channel attacks. Unfortunately, existing randomization proposals cannot be sucessfully applied to processors’ cache hierarchies due to the overhead added when dealing with coherency and virtual memory. In this paper, we solve existing limitations of hardware randomization approaches and propose a cost-effective randomization implementation to the whole cache hierarchy of a Linux-capable RISC-V processor.
dc.description.peerreviewedPeer Reviewed
dc.description.sponsorshipThis work has been supported by the European HiPEAC Network of Excellence, by the Spanish Ministry of Economy and Competitiveness (contract TIN2015-65316-P), and by Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017- SGR-1328). The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total cost eligible. We also thank Red-RISCV for the efforts to promote activities around open hardware. This work has received funding from the EU Horizon2020 programme under grant agreement no. 871467 (SELENE). M. Doblas has been partially supported by the Agency for Management of University and Research Grants (AGAUR) of the Government of Catalonia under Beques de Col·laboració d’estudiants en departaments universitaris per al curs 2019- 2020. V. Kostalabros has been partially supported by the Agency for Management of University and Research Grants (AGAUR) of the Government of Catalonia under Ajuts per a la contractació de personal investigador novell fellowship number 2019FI_ B01274. M. Moreto has been partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under Ramón y Cajal fellowship number RYC- 2016-21104.
dc.description.versionPostprint (published version)
dc.format.extent7 p.
dc.identifier.citationDoblas, M. [et al.]. Enabling hardware randomization across the cache hierarchy in Linux-Class processors. A: Workshop on Computer Architecture Research with RISC-V. "Fourth Workshop on Computer Architecture Research with RISC-V (CARRV 2020): Virtual Workshop, Friday, May 29th, 2020: co-located with ISCA 2020". 2020, p. 1-7.
dc.identifier.urihttps://hdl.handle.net/2117/190692
dc.language.isoeng
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/2017 SGR 1414
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/2017-SGR-1328
dc.relation.projectidinfo:eu-repo/grantAgreement/AEI/RYC-2016-21104
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/871467/EU/SELENE: Self-monitored Dependable platform for High-Performance Safety-Critical Systems/SELENE
dc.relation.publisherversionhttps://carrv.github.io/2020/papers/CARRV2020_paper_8_Doblas.pdf
dc.rights.accessOpen Access
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subjectÀrees temàtiques de la UPC::Informàtica::Seguretat informàtica
dc.subject.lcshCache memory
dc.subject.lcshComputer security
dc.subject.lemacMemòria cau
dc.subject.lemacSeguretat informàtica
dc.subject.otherSecure-cache design
dc.subject.otherCache-set randomization
dc.subject.otherCache side-channel attacks
dc.subject.otherRISC-V processor
dc.titleEnabling hardware randomization across the cache hierarchy in Linux-Class processors
dc.typeConference report
dspace.entity.typePublication
local.citation.authorDoblas, M.; Kostalabros, I.; Moreto, M.; Hernández, C.
local.citation.contributorWorkshop on Computer Architecture Research with RISC-V
local.citation.endingPage7
local.citation.publicationNameFourth Workshop on Computer Architecture Research with RISC-V (CARRV 2020): Virtual Workshop, Friday, May 29th, 2020: co-located with ISCA 2020
local.citation.startingPage1
local.identifier.drac28660551

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