While the importance of parallel hardware architectures has been increasing over the decades, software tends to be one step behind. In the testing and reliability field, noncommercial software is often designed with few to no parallelism in mind. In this paper, we focus on a toolchain that allows us to measure the stress metrics of large SoC through the analysis of enormous Value Change Dump files produced by the testing and simulation equipment. In this toolchain, we concentrate on speeding up the analysis and making the entire process more automatic through pipeline and parallelization techniques. We tested the resulting Burn-In test application on a real chip, developed by STMicroelectronics.