Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification

dc.contributor.authorEspinosa, Jaime
dc.contributor.authorHernandez, Carles
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorde Andres, David
dc.contributor.authorRuiz, Juan C.
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2016-05-24T09:21:51Z
dc.date.available2016-05-24T09:21:51Z
dc.date.issued2015
dc.description.abstractIncreasingly complex microcontroller designs for safety-relevant automotive systems require the adoption of new methods and tools to enable a cost-effective verification of their robustness. In particular, costs associated to the certification against the ISO26262 safety standard must be kept low for economical reasons. In this context, simulation-based verification using instruction set simulators (ISS) arises as a promising approach to partially cope with the increasing cost of the verification process as it allows taking design decisions in early design stages when modifications can be performed quickly and with low cost. However, it remains to be proven that verification in those stages provides accurate enough information to be used in the context of automotive microcontrollers. In this paper we analyze the existing correlation between fault injection experiments in an RTL microcontroller description and the information available at the ISS to enable accurate ISS-based fault injection.
dc.description.peerreviewedPeer Reviewed
dc.description.sponsorshipThe research leading to these results has received funding from the ARTEMIS Joint Undertaking VeTeSS project under grant agreement number 295311. This work has also been funded by the Ministry of Science and Technology of Spain under contract TIN2012-34557 and HiPEAC. Jaume Abella is partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717.
dc.description.versionPostprint (author's final draft)
dc.format.extent6 p.
dc.identifier.doi10.1145/2744769.2744798
dc.identifier.issn0738-100X
dc.identifier.urihttps://hdl.handle.net/2117/87263
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TIN2012-34557
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//RYC-2013-14717/ES/RYC-2013-14717/
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7167224&openedRefinements%3D*%26filter%3DAND%28NOT%284283010803%29%29%26pageNumber%3D8%26rowsPerPage%3D100%26queryText%3DDesign+Automation+Conference
dc.rights.accessOpen Access
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshSimulation and Modeling
dc.subject.lcshAutomotive technology
dc.subject.lemacElectrònica--Automòbils
dc.subject.lemacSimulació, Mètodes de
dc.subject.otherAutomotive engineering
dc.subject.otherBenchmark testing
dc.subject.otherRobustness
dc.titleAnalysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification
dc.typeConference report
dspace.entity.typePublication
local.citation.contributor52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 8-12 June 2015, San Francisco, CA
local.citation.endingPage6
local.citation.publicationName2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)
local.citation.startingPage1
local.personalitzacitaciotrue

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