Analog VLSI implementation of kernel-based classifiers

Abstract

Kernel-based classifiers are neural networks (radial basis functions) where the probability densities of each class of data are first estimated, to be used thereafter to approximate Bayes boundaries between classes. Such an algorithm however involves a large number of operations, and its parallelism makes it an ideal candidate for a dedicated VLSI implementation. The authors present in this paper the architecture for a dedicated processor for kernel-based classifiers, and the implementation of the original cells.