Variable-Frequency Grid-Sequence Detector Based on a Quasi-Ideal Low-Pass Filter Stage and a Phase-Locked Loop

dc.contributor.authorRobles Sestafe, Eider
dc.contributor.authorCeballos Recio, Salvador
dc.contributor.authorPou Félix, Josep
dc.contributor.authorMartin, Jose Luis
dc.contributor.authorZaragoza Bertomeu, Jordi
dc.contributor.authorIbáñez, P.
dc.contributor.groupUniversitat Politècnica de Catalunya. (TIEG) - Terrassa Industrial Electronics Group
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2010-12-13T10:10:32Z
dc.date.available2010-12-13T10:10:32Z
dc.date.created2010-09
dc.date.issued2010-09
dc.description.abstractThis paper proposes a filtered-sequence phase-locked loop (FSPLL) structure for detection of the positive sequence in three-phase systems. The structure includes the use of the Park transformation and moving average filters (MAF). Performance of the MAF is mathematically analyzed and represented in Bode diagrams. The analysis allows a proper selection of the window width of the optimal filter for its application in the dq transformed variables. The proposed detector structure allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF eliminates completely any oscillation multiple of the frequency for which it is designed; thus, this algorithm is not affected by the presence of imbalances or harmonics in the electrical grid. Furthermore, the PLL includes a simple-frequency detector that makes frequency adaptive the frequency depending blocks. This guarantees the proper operation of the FSPLL under large frequency changes. The performance of the entire PLL-based detector is verified through simulation and experiment. It shows very
dc.description.peerreviewedPeer Reviewed
dc.description.versionPostprint (published version)
dc.format.extent12 p.
dc.identifier.citationRobles, E. [et al.]. Variable-Frequency Grid-Sequence Detector Based on a Quasi-Ideal Low-Pass Filter Stage and a Phase-Locked Loop. "IEEE transactions on power electronics", Setembre 2010, vol. 25, núm. 10, p. 2552-2563.
dc.identifier.doi10.1109/TPEL.2010.2050492
dc.identifier.issn0885-8993
dc.identifier.urihttps://hdl.handle.net/2117/10551
dc.language.isoeng
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05466221
dc.rights.accessOpen Access
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència
dc.subject.lcshFrequency discriminators
dc.subject.lcshElectric current converters
dc.subject.lcshPhase-locked loops
dc.subject.lemacConvertidors de freqüència
dc.subject.lemacDetectors
dc.titleVariable-Frequency Grid-Sequence Detector Based on a Quasi-Ideal Low-Pass Filter Stage and a Phase-Locked Loop
dc.typeArticle
dspace.entity.typePublication
local.citation.authorRobles, E.; Ceballos, S.; Pou, J.; Martin, J.; Zaragoza, J.; Ibáñez, P.
local.citation.endingPage2563
local.citation.number10
local.citation.publicationNameIEEE transactions on power electronics
local.citation.startingPage2552
local.citation.volume25
local.identifier.drac4414646

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