High-performance applications are highly sensitive to memory performance characteristics. While programs with comparatively low memory-to-computation ratio are less likely to be hampered by limited memory bandwidth, most parallel applications will be severely impacted by the absence of hardware support for low-latency inter-thread synchronization and data sharing. In this paper, we report a design exploration that sought to identify the cache configuration that maximizes performance of task parallel OpenMP workloads running on a Linux-capable 32-core RISC-V system. We show that, under the constraints of a U200 Alveo FPGA, the best single-level cache configuration consists in 160 KB of coherent, core-private data caches, with a 32/128 split among instruction and program data. With such configuration, we have achieved speedups of up to 28x and 19x for the nbody and cholesky applications, respectively.