Exploring the voltage divider approach for accurate memristor state tuning
| dc.contributor.author | Vourkas, Ioannis |
| dc.contributor.author | Gomez, Jorge |
| dc.contributor.author | Abusleme, Angel |
| dc.contributor.author | Vasileiadis, Nikolaos |
| dc.contributor.author | Sirakoulis, Georgios |
| dc.contributor.author | Rubio Sola, Jose Antonio |
| dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
| dc.date.accessioned | 2017-07-28T11:17:58Z |
| dc.date.issued | 2017 |
| dc.description.abstract | The maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multilevel programming. In this direction, we explore the voltage divider (VD) approach for highly controllable multi-state SET memristor tuning. We present the theoretical basis of operation, the main advantages and weaknesses. We finally propose an improved closed-loop VD SET scheme to tackle the variability effect and achieve <1% tuning precision, on average 3× faster than another accurate tuning algorithm of the recent literature. |
| dc.description.peerreviewed | Peer Reviewed |
| dc.description.version | Postprint (published version) |
| dc.format.extent | 4 p. |
| dc.identifier.citation | Vourkas, I., Gomez, J., Abusleme, A., Vasileiadis, N., Sirakoulis, G., Rubio, A. Exploring the voltage divider approach for accurate memristor state tuning. A: Latin American Symposium on Circuits and Systems. "2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS 2017): Bariloche, Argentina: 20-23 February 2017". Bariloche: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 1-4. |
| dc.identifier.doi | 10.1109/LASCAS.2017.7948043 |
| dc.identifier.isbn | 978-1-5090-5859-4 |
| dc.identifier.uri | https://hdl.handle.net/2117/107035 |
| dc.language.iso | eng |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TEC2013-45638-C3-2-R/ES/APROXIMACION MULTINIVEL AL DISEÑO ORIENTADO A LA FIABILIDAD DE CIRCUITOS INTEGRADOS ANALOGICOS Y DIGITALES/ |
| dc.relation.publisherversion | http://ieeexplore.ieee.org/document/7948043/ |
| dc.rights.access | Restricted access - publisher's policy |
| dc.subject | Àrees temàtiques de la UPC::Enginyeria elèctrica::Maquinària i aparells elèctrics |
| dc.subject.lcsh | Circuits elèctrics |
| dc.subject.lemac | Electric circuits |
| dc.subject.other | Memristor |
| dc.subject.other | Resistive switching |
| dc.subject.other | Resistive RAM |
| dc.subject.other | Tuning |
| dc.subject.other | Voltage divider |
| dc.subject.other | Multi-level storage |
| dc.title | Exploring the voltage divider approach for accurate memristor state tuning |
| dc.type | Conference report |
| dspace.entity.type | Publication |
| local.citation.author | Vourkas, I.; Gomez, J.; Abusleme, A.; Vasileiadis, N.; Sirakoulis, G.; Rubio, A. |
| local.citation.contributor | Latin American Symposium on Circuits and Systems |
| local.citation.endingPage | 4 |
| local.citation.publicationName | 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS 2017): Bariloche, Argentina: 20-23 February 2017 |
| local.citation.pubplace | Bariloche |
| local.citation.startingPage | 1 |
| local.identifier.drac | 21209938 |
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