The ASIC industry is experiencing a massive change in the recent years with more and more small and medium business entering the custom ASIC development. This trend is fueled by the recent open hardware movement and relevant government and privately funded initiatives. These new developments can open new opportunities in the space sector, which is traditionally characterised by very low volumes and very high non-recurrent (NRE) costs, if we can show that the produced chips have favourable radiation properties. In this ACM SRC entry, we describe the design and tape-out of Space Shuttle, the first test chip for the evaluation of the suitability of the SkyWater 130nm PDK and the OpenLane EDA toolchain using the Google/E-fabless shuttle run for future space processors.