Abstract—Process variability and environmental fluctuations deeply affect the digital circuits performance in many different ways, one of them, the data processing time which may cause error on synchronous digital circuits due to underestimated time violations. This situation is commonly avoided adding time margins to the clock signal making it larger than nominal worstcase data process time, penalizing the global performance. In this paper a new mechanism for compensating both environmental fluctuations and process parameters variations effects on digital circuits is presented. The environmental compensation mechanism regenerates the clock signal for a pipelined system stages adding a compensated skew component depending on the local environmental conditions of every one of these stages. The process variations are corrected with a calibration circuit which adjusts the clock period in every stage taking into account its particular static deviations.