Multicores for critical real-time embedded systems (CRTES) may experience interference across tasks running in different cores when accessing shared hardware resources such as shared caches and memory controllers. Precise interference diagnostics (e.g., what task interferes what other task and how much) are key for the optimization and validation of safety-related real-time applications during development, and to diagnose overruns during operation. The SafeSU statistics unit has been proposed recently for that purpose, and proven successful for systems-on-chip (SoCs) where interference can occur at a single centralized locations (e.g., a bus). However, it is unable to monitor interference in multiple-level interconnects, especially if request ownership is not available. This paper extends the SafeSU to 2-level interconnects (SafeSU-2 L), where interference can occur in the bus connecting the cores with a shared second level cache (L2C), and in the DDR4 memory controller serving L2C misses, with the latter losing track of the actual core issuing each DDR4 request. In particular, the SafeSU-2 L monitors some additional signals from the buses and caches to infer what core interferes what other core in any of the shared resources. Moreover, the SafeSU-2 L is integrated and tested on a 4-core version of the commercial CAES Gaisler NOEL-XCKU-EX space SoC.