Reusable Verification Environment for a RISC-V Vector Accelerator

Abstract

This paper presents a reusable verification environment developed for the verification of an academic RISC-V based vector accelerator that operates with long vectors. In order to be used across diverse projects, this infrastructure intends to be independent of the interface used for connecting the accelerator to the scalar processor core. We built a verification infrastructure consisting of a Universal Verification Environment (UVM) which is capable of validating the design performing co-simulation of the vector instructions. Moreover, we provided a set of tests and an automated test generation, simulation and error reporting infrastructure. This paper shares our experience on verifying a complex accelerator used in two distinct projects, with different interfaces.