New semiconductor technologies for advanced applications are more prone to defects and imperfections related, among many different causes, to the manufacturing process, aging and cross-talks. These phenomena negatively affect the circuit’s timing and can be effectively modeled by means of the delay fault model, both in the form of transition delay faults (TDFs) and path delay faults (PDFs). While delay testing is currently supported by commercial ATPG tools, functional testing covering delay faults is not widely adopted, mainly because of the high cost for test generation. Functional test in the form of Software-Based Self-Test (SBST), however, is an attractive solution since it can be performed at-speed with reduced power consumption, making it a suitable in-field test solution. In my research, I present systematic methodologies for the development of highly effective Self-Test Libraries (STLs) targeting transition and path delay faults on pipelined processor cores. Results demonstrate that fault coverages for transition and path delay fault models is improved on an open source RISC-V core.