This paper presents the SEPELYNS architecture that permits to in- terconnect multiple spiking neurons focused on hardware implementations. SEPELYNS can connect millions of neur ons with thousands of synapses per neuron in a layered fabric that provides some capabilities such as connectivity, expansion, flexibility, bio-plausibility and reusing of resources that allows si- mulation of very large networks. We presen t the three layers of this architecture (neuronal, network adapters and networks on chip layers) and explain its per- formance parameters such as throughput, latency and hardware resources. Some application examples of large neural networks on SEPELYNS are studied; these will show that use of on-chip parallel networks could permit the hardware simulation of populations of spiking neurons.