In the last decade we have witnessed great advances in the integrated circuits technology. Those advances make it possible nowadays for the manufacturing, at reasonable prices of MOS technology memories that are faster than the microprocessors. These memories allow, thus several accesses in each microprocessor cycle. Therefore it seems reasonable to use the to reduce the memory interference in multimicroprocessor systems.

In this paper we present two mathematical models useful in the approximate evaluation of the memory interference. The results for both model concide. We also compare the with experimental valuesobtained by simulation.