Using LUT-specific delays to mitigate biases in delay-based PUFs and increase area efficiency on FPGAs

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dc.contributor.authorFeiten, Linus
dc.contributor.authorSauer, Matthias
dc.contributor.authorBecker, Bernd
dc.coverage.spatialeast=2.11563799999999; north=41.38479239999999; name=Zona Universitària-Escola T S d'Enginyers, 08028 Barcelona, Espanya
dc.date.accessioned2017-01-17T09:11:11Z
dc.date.issued2016-11-14
dc.format.extent1 p.
dc.identifier.urihttps://hdl.handle.net/2117/99398
dc.language.isoeng
dc.rights.accessRestricted access - confidentiality agreement
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshEmbedded computer systems--Congresses
dc.subject.lcshIntegrated circuits
dc.subject.lcshComputer networks--Security measures
dc.subject.lemacSistemes integrats -- Congressos
dc.subject.lemacCircuits integrats
dc.subject.lemacSeguretat informàtica -- Congressos
dc.titleUsing LUT-specific delays to mitigate biases in delay-based PUFs and increase area efficiency on FPGAs
dc.typeConference report
dspace.entity.typePublication

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6th Conference on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2016), Barcelona, 14-16 November, 2016