Functional and performance validation of high-performance safety-related hardware platforms require generating specific traffic patterns in the network-on-chip (NoC) to test IP components and their integration. Software-only tests offer indirect control on the NoC traffic and are subject to numerous constraints (e.g., the inability to inject bursty traffic synchronously since cores may not be able to generate it explicitly). Instead, hardware traffic injectors, such as the SafeTI are much more versatile and controllable.This paper presents how our SafeTI hardware traffic injector can be used for the validation of an L2 cache in a safety-relevant space MPSoC by Frontgrade Gaisler, and how such validation process allowed identifying a hard-to-detect design flaw that led to decreased available cache space. Overall, our experience shows a specific application of the SafeTI for black-box IP validation and a success story for that application.