Exploració per autor "Zulianello, Marco"

Ara es mostren els items 1-5 de 5

    • Contention-aware performance monitoring counter support for real-time MPSoCs 

      Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Andersson, Jan; Patte, Mathieu; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Comunicació de congrés
      Accés obert
      Tasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ...

    • Data bus slicing for contention-free multicore real-time memory systems 

      Jalle Ibarra, Javier; Quiñones, Eduardo; Abella Ferrer, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
      Accés obert
      Memory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ...

    • Deconstructing bus access control policies for real-time multicores 

      Jalle Ibarra, Javier; Abella Ferrer, Jaume; Quiñones, Eduardo; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Multicores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ...

    • Seeking time-composable partitions of tasks for COTS multicore processors 

      Fernández, Gabriel; Abella Ferrer, Jaume; Quiñones, Eduardo; Fossati, Luca; Zulianello, Marco; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Comunicació de congrés
      Accés obert
      The timing verification of real-time single core systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes ...

    • Validating a timing simulator for the NGMP multicore processor 

      Jalle Ibarra, Javier; Abella Ferrer, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (European Space Agency (ESA), 2016)
      Text en actes de congrés
      Accés obert
      Timing simulation is a key element in multicore systems design. It enables a fast and cost effective design space exploration, allowing to simulate new architectural improvements without requiring RTL abstraction levels. ...