Now showing items 1-5 of 5

    • Communication reduction techniques in numerical methods and deep neural networks 

      Zhuang, Sicong (Universitat Politècnica de Catalunya, 2019-11-28)
      Doctoral thesis
      Open Access
      Inter-node communication has turned out to be one of the determining factors of the performance on modern HPC systems. Furthermore, the situation only gets worse with the ever-incresing size of the cores involved. Hence, ...
    • Evaluating scientific workflow execution on an asymmetric multicore processor 

      Pietri, Ilia; Zhuang, Sicong; Casas, Marc; Moreto Planas, Miquel; Sakellariou, Rizos (Springer, 2018-02)
      Conference lecture
      Open Access
      Asymmetric multicore architectures that integrate different types of cores are emerging as a potential solution for good performance and power efficiency. Although scheduling can be improved by utilizing an appropriate set ...
    • Improving The Robustness Of The Register File: a Register File Cache Architecture 

      Zhuang, Sicong (Universitat Politècnica de Catalunya, 2014-09-09)
      Master thesis
      Open Access
      This thesis exploits a multi-band cache-like register file architecture to mitigate the potential damage caused by process variations and soft error (single event upsets). An quantitative analysis is conducted to measure ...
    • Iteration-fusing conjugate gradient 

      Zhuang, Sicong; Casas, Marc (Association for Computing Machinery (ACM), 2017-06)
      Conference lecture
      Open Access
      This paper presents the Iteration-Fusing Conjugate Gradient (IFCG) approach which is an evolution of the Conjugate Gradient method that consists in i) letting computations from different iterations to overlap between them ...
    • Linompss – A Linear Algebra Library on OMPSs 

      Zhuang, Sicong (Barcelona Supercomputing Center, 2015-05-05)
      Conference report
      Open Access
      Exascale performance will require massive parallelism and asynchronous execution (DARPA, DOE, EESI2). The former pertains to the design choice to increase hardware performance through growing core counts. The latter ensures ...