Browsing by Author "Vilanova, Lluís"
Vilanova, Lluís (Barcelona Supercomputing Center, 2019)
Vilanova, Lluís; Ben-Yehuda, Muli; Navarro, Nacho; Etsion, Yoav; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
Restricted access - publisher's policyToday's complex software systems are neither secure nor reliable. The rudimentary software protection primitives provided by current hardware forces systems to run many distrusting software components (e.g., procedures, ...
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures Álvarez Martí, Lluc; Vilanova, Lluís; Moreto Planas, Miquel; Casas, Marc; González Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2015)
Open AccessThe increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a ...
Tanasic, Ivan; Vilanova, Lluís; Jorda, Marc; Cabezas, Javier; Gelado Fernandez, Isaac; Navarro, Nacho; Hwu, Wen-mei W. (Association for Computing Machinery (ACM), 2013)
Restricted access - publisher's policyAs a basic building block of many applications, sorting algorithms that efficiently run on modern machines are key for the performance of these applications. With the recent shift to using GPUs for general purpose compuing, ...
Álvarez Martí, Lluc; Vilanova, Lluís; González Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguadé Parra, Eduard (2015-01-01)
Open AccessCache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce ...