Now showing items 1-4 of 4

    • Automatic safe data reuse detection for the WCET analysis of systems with data caches 

      Segarra Flor, Juan; Cortadella, Jordi; Gran Tejero, Rubén; Viñals Yúfera, Victor (Institute of Electrical and Electronics Engineers (IEEE), 2020-10-19)
      Article
      Open Access
      Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents ...
    • Near-optimal replacement policies for shared caches in multicore processors 

      Díaz Maag, Javier; Ibáñez Marín, Pablo; Monreal Arnal, Teresa; Viñals Yúfera, Victor; Llaberia Griñó, José M. (2021-10)
      Article
      Open Access
      An optimal replacement policy that minimizes the miss rate in a private cache was proposed several decades ago. It requires knowing the future access sequence the cache will receive. There is no equivalent for shared caches ...
    • Pronóstico de capacidad efectiva y prestaciones en una cache no volátil de último nivel 

      Escuín Blasco, Carlos; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Victor (Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), 2021)
      Conference report
      Open Access
      La degradación debida a las escrituras que sufren las bitcells implementadas con tecnologi´as de memoria no volátil (NVM) es uno de los principales escollos que se presentan a la hora de construir la cache de último nivel ...
    • STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption 

      Escuín Blasco, Carlos; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Viñals Yúfera, Victor; Ibáñez Marín, Pablo (European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2019)
      Conference lecture
      Open Access
      Current applications demand larger on-chip memory capacity since off-chip memory accesses be-come a bottleneck. However, if we want to achieve this by scaling down the transistor size of SRAM-based Last-Level Caches (LLCs) ...