Now showing items 1-2 of 2

  • Hardware synthesis for asynchronous communications mechanisms 

    Costa Gorgônio, Kyller; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Conference report
    Open Access
    Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed concurrent processes. In this work an automatic method for synthesis of re-reading ACMs is ...
  • Implementación RTL/Verilog de un procesador de shader para una GPU 

    Pizarro Calvo, Iván (Universitat Politècnica de Catalunya, 2012-06-20)
    Master thesis (pre-Bologna period)
    Open Access
    Implementación RTL/Verilog de un procesador de shader para una GPU. Forma parte del proyecto ATTILA.