Browsing by Author "Veidenbaum, Alex"
Now showing items 1-5 of 5
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A content aware integer register file organization
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Conference report
Open AccessA register file is a critical component of a modern superscalar processor. It has a large number of entries and read/write ports in order to enable high levels of instruction parallelism. As a result, the register file's ... -
A novel architecture for large windows processors
(2007-11)
Research report
Open AccessSeveral processor architectures with large instruction windows have been proposed. They improve performance by maintaining hundreds of instructions in flight to increase the level of instruction parallelism (ILP). Such ... -
Direct instruction wakeup for out-of-order processors
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Conference report
Open AccessInstruction queues consume a significant amount of power in high-performance processors, primarily due to instruction wakeup logic access to the queue structures. The wakeup logic delay is also a critical timing parameter. ... -
Fast speculative address generation and way caching for reducing L1 data cache energy
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
Conference report
Open AccessL1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access latency can be affected as well, leading to ... -
Power-aware load balancing of large scale MPI applications
(Institute of Electrical and Electronics Engineers (IEEE), 2009)
Conference report
Open AccessPower consumption is a very important issue for HPC community, both at the level of one application or at the level of whole workload. Load imbalance of a MPI application can be exploited to save CPU energy without penalizing ...
