Browsing by Subject "VHDL (Computer hardware description language)"
Now showing items 1-20 of 33
-
A RF generator based on a FPGA system
(Universitat Politècnica de Catalunya, 2014-03-06)
Master thesis
Open Access
Covenantee: Beijing hang kong hang tian da xue[ANGLÈS] This work is part of ongoing research conducted at Beihang University relating to signal generating. The primary objective of this thesis was to develop a flexible, high-performance Radio Frequency (RF) generator ... -
AER communication for spiking neural network emulation on a microprocessor
(Universitat Politècnica de Catalunya, 2023-10-17)
Bachelor thesis
Open AccessEn aquest treball s'estudia un sistema de comunicació basat en el protocol AER (Address event representation) per a una xarxa neuronal del tipus spiking. Per fer-ho, en aquest projecte es dissenyen, utilitzant VHDL, les ... -
AER-RT: Interfaz de Red con Topología en Anillo para SNN Multi-FPGA
(Universitat Politècnica de Catalunya, 2013-07-08)
Master thesis
Open Access[ANGLÈS] This thesis presents AER-RT network interface, a network interface designed to work together a Multiprocessor System (MPS) and create an efficient and scalable multi-chip SNN network. The objective of AER-RT is ... -
Analysis of the Task Superscalar architecture hardware design
(Springer, 2013)
Conference report
Open AccessIn this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task ... -
Aplicaciones didácticas de PLD/FPGA para las asignaturas de sistemas digitales
(Universitat Politècnica de Catalunya, 2012-03-07)
Bachelor thesis
Open AccessEste proyecto es una guía destinada a los futuros alumnos de la asignatura CSD que se imparte en el grado en Ingeniería de Sistemas de Telecomunicaciones en la EETAC y para personas que se inicien en el lenguaje de ... -
Comparativa d'implementació hardware vs software en un sistema de processat d'imatge per a detecció de cares
(Universitat Politècnica de Catalunya, 2016-06)
Bachelor thesis
Open AccessIn this project two implementations of a face detection system, one of them based on hardware and the other on software, have been developed. The main goal is to compare both implementations and determine the advantages ... -
Comunicación y procesado de datos entre un ordenador y una FPGA
(Universitat Politècnica de Catalunya, 2015-10-15)
Master thesis
Restricted access - confidentiality agreement -
Desenvolupament d'un sistema complet de càmera digital a la placa d'avaluació de FPGAs DE2
(Universitat Politècnica de Catalunya, 2020-09)
Bachelor thesis
Restricted access - confidentiality agreement -
Design and implementation of an ARMv4 tightly coupled multicore in VHDL and validation on a FPGA
(Universitat Politècnica de Catalunya / Technische Universität Berlin, 2012-07-09)
Master thesis (pre-Bologna period)
Open Access[ANGLÈS] On one hand, few years ago increasing the clock speed was the preferred tactic by manufacturers to gradually increase the performance of computers. However, from certain speeds there are some limitations. Some ... -
Design of single precision float adder (32-bit numbers) according to IEEE 754 standard using VHDL
(Universitat Politècnica de Catalunya / Slovenská Technická Univerzita v Bratislave, 2012-04-25)
Master thesis
Open Access
Covenantee: Slovenská technická univerzita v Bratislave[ANGLÈS] Floating Point arithmetic is by far the most used way of approximating real number arithmetic for performing numerical calculations on modern computers. Each computer had a different arithmetic for long time: ... -
Development of the readout software for flexible, high-density neural probes
(Universitat Politècnica de Catalunya, 2018-06)
Bachelor thesis
Open AccessThis project has been developed in Neuro-Electronic Research Flandes (NERF), with the main purpose of developing a readout software based on the open-source project Open Ephys, consisting in commercial silicon chips for ... -
Diseño e implementación de un dispositivo reproductor / grabador basado en una FPGA
(Universitat Politècnica de Catalunya, 2016-05)
Master thesis (pre-Bologna period)
Restricted access - confidentiality agreement -
Disseny d'un protocol de comunicació en sèrie sobre circuits integrats de la família Zynq 7000 de Xilinx
(Universitat Politècnica de Catalunya, 2020-01)
Bachelor thesis
Open AccessThe Zybo board is a powerful tool for developing Systems based on the Zynq-7000 SoC. They can be used in many environments, including educational. However, currently there are no available systems to connect several boards ... -
Disseny de generadors de senyal FM reconfigurable per a radars CW basats en la tècnica DDS (Síntesi Digital Directa)
(Universitat Politècnica de Catalunya, 2018-06)
Bachelor thesis
Restricted access - confidentiality agreementThe aim of the project is to design and develope a signal generator for high resolution CW-FM radars. The signal is a linear FM called chirp. The object of this generator is to be versatile and reconfigurable, in order to ... -
Disseny i implementació d'un transceptor super-regeneratiu QPSK
(Universitat Politècnica de Catalunya, 2013-07-05)
Master thesis
Open Access[ANGLÈS] This project consists on the design and the implementation of a radio frequency transceiver. A transceiver is a device which is able to be a transmitter and a receiver and, therefore, it is suitable for commuting ... -
Disseny i Implementació d'una jerarquia de memòria en un processador MIPS
(Universitat Politècnica de Catalunya, 2013-06-18)
Bachelor thesis
Open Access[CATALÀ] Primer s'explicarà breument l'arquitectura d'un MIPS, la jerarquia de memòria i el funcionament de la cache. Posteriorment s'explicarà com s'ha dissenyat i implementat una jerarquia de memòria per a un MIPS ... -
Disseny VHDL de la unitat de control d'un acceleròmetre
(Universitat Politècnica de Catalunya, 2013-05-28)
Master thesis (pre-Bologna period)
Open Access[ANGLÈS] An accelerometer is an instrument that calculates acceleration forces, using his inertial movement towards some known coordinates. There are quite a few technologies and designs and all of them have as a prime ... -
Estudi, modelació i síntesi sobre FPGA d'un sistema de detecció de contorns per a imatges HDR
(Universitat Politècnica de Catalunya, 2012-06-26)
Master thesis (pre-Bologna period)
Open Access
Covenantee: Concordia University[ENGLISH] The purpose of this study was to perform the hardware description in VHDL language of an Edge Detection system based in Sobel operator and Multifiltering for a Virtex-5 FPGA. The procedure of the algorithm was ... -
Flexible FPGA based platform for variable rate signal generation
(Universitat Politècnica de Catalunya / Technical University of Denmark, 2013-09-10)
Master thesis (pre-Bologna period)
Open Access
Covenantee: Danmarks tekniske universitet[ANGLÈS] In any digital communication system, data prior to transmission have to be line coded into a form that is best suited for the channel and at the same time minimize number of occurring bit errors at the receiver. ... -
FPGA-based digital signal processing for an optical interferometer thermometer
(Universitat Politècnica de Catalunya, 2023-07-04)
Bachelor thesis
Open Access
Covenantee: Institut d'Estudis Espacials de Catalunya / ESA European Astronaut Centre (EAC)This thesis takes part in the LIRA project. This project is an ESA's contract, with the aim to implement a fiber optic temperature sensor which fulfils the requirements of the LISA project, which is based in the detection ...
