Browsing by Author "Stavrou, Kyriakos"

Now showing items 1-4 of 4

    • Accurate off-line phase classification for HW/SW co-designed processors 

      Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María (Association for Computing Machinery (ACM), 2014)
      Conference report
      Open Access
      Evaluation techniques in microprocessor design are mostly based on simulating selected application's samples using a cycle-accurate simulator. These samples usually correspond to different phases of the application stream. ...

    • Analysis of CPI variance for dynamic binary translators/optimizers modules 

      Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María (IEEE, 2012)
      Conference report
      Restricted access - publisher's policy
      Dynamic Binary Translators and Optimizers (DBTOs) have been established as a hot research topic. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW co-designed ...

    • HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation 

      Kumar, Rakesh; Cano, José; Brankovic, Aleksandar; Pavlou, Demos; Stavrou, Kyriakos; Gibert Codina, Enric; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Conference report
      Open Access
      Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. ...

    • Quantitative characterization of the software layer of a HW/SW co-designed processor 

      Cano Reyes, José; Kumar, Rakesh; Brankovic, Aleksandar; Pavlou, Demos; Stavrou, Kyriakos; Gibert Codina, Enric; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary ...