Browsing by Contributor "Sonmez, Nehir"

Now showing items 1-5 of 5

    • A Vector processing unit implementation for RISC-V vector extension: Functional verification and assertions on submodules 

      Valente, Luca (Universitat Politècnica de Catalunya, 2020-09)
      Master thesis
      Open Access
      Power dissipation and Energy consumption of digital circuits has emerged as an important design parameter in the evaluation of microelectronic circuits. This has led electronic architects to value Parallel Architectures ...

    • Design under test interface implementation and stimulus in the verification of a RISC-V vector accelerator 

      Jiménez Arador, Víctor (Universitat Politècnica de Catalunya, 2021)
      Master thesis
      Restricted access - author's decision
      Covenantee:   Barcelona Supercomputing Center
      The production of a microprocessor is one of the most complex and expensive processes in the industry these days. These high costs are why big companies dedicate most of their efforts to design verification during the ...

    • Infrastructure and functional correctness in the verification of a RISC-V vector accelerator 

      Rodríguez Pérez, Mario (Universitat Politècnica de Catalunya, 2022-01-26)
      Master thesis
      Restricted access - author's decision
      Covenantee:   Barcelona Supercomputing Center
      When we talk about hardware development, many efforts are made to tape out a bug-free design. The hardware fabrication process costs enormous amounts of money to the companies, so they can not afford to produce faulty ...

    • Multicore architecture prototyping on reconfigurable devices 

      Arcas Abella, Oriol (Universitat Politècnica de Catalunya, 2016-04-15)
      Doctoral thesis
      Open Access
      In the the last decades several performance walls were hit. The memory wall and the power wall are limiting the performance scaling of digital microprocessors. Homogeneous multicores rely on thread-level parallelism, which ...

    • Verification of a floating point reduction unit 

      Díaz Ortega, Iván (Universitat Politècnica de Catalunya, 2021-07-01)
      Bachelor thesis
      Open Access
      This thesis goes around the effort made to verify a submodule of a vector processing unit or VPU. This submodule is the one in charge of performing vector reductions, and due to the nature of some of the reductions, an ...