Now showing items 1-9 of 9

    • ADAM : an efficient data management mechanism for hybrid high and ultra-low voltage operation caches 

      Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (2012)
      Conference report
      Restricted access - publisher's policy
      Semiconductor technology evolution enables the design of ultra-low-cost chips (e.g., below 1 USD) required for new market segments such as environment, urban life and body monitoring, etc. Recently, hybrid-operation (high ...
    • Caracterització i modelació de memristors sota ressonància estocàstica per aplicacions en seguretat a nivell de hardware (EEL) 

      Munar Sarria, Gabriel (Universitat Politècnica de Catalunya, 2022-10-24)
      Master thesis
      Open Access
      Aquest projecte ha sigut possible gràcies a la proposta de l’equip d’investigació del Departament d’Electrònica de la Universitat Politècnica de Catalunya. Es centra en l’àrea de la seguretat en el hardware (Hardware ...
    • Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations 

      Jaksic, Zoran; Canal Corretger, Ramon (2012-12)
      Article
      Restricted access - publisher's policy
      We explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write margin, and leakage for future 10-nm FinFETs. Process variations are based on the ITRS and modeled at device (TCAD) level. ...
    • Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs 

      Jaksic, Zoran; Canal Corretger, Ramon (IEEE Computer Society Publications, 2012)
      Conference report
      Restricted access - publisher's policy
      In this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access ...
    • Estudi de viabilitat de l'actualització del HW d'una impressora de llarg format 

      Bover Centelles, Enric (Universitat Politècnica de Catalunya, 2021-01)
      Bachelor thesis
      Open Access
      Avui en dia es busca optimitzar el màxim possible els recursos hardware. Actualment en alguns dels projectes d'HP hi ha un malbaratament de l'ús de les memòries que incorporen les FPGA que utilitzen ja que no hi ha cap ...
    • Memòries 

      Amat Girbau, Josep; Ferrer, F. (Asociación de Técnicos de Informática, 1980)
      Article
      Open Access
    • Memòries externes 

      Puigjaner Trepat, Ramón (Asociación de Técnicos de Informática, 1980)
      Article
      Open Access
    • Power-efficient noise-Induced reduction of ReRAM cell’s temporal variability effects 

      Ntinas, Vasileios; Rubio Sola, Jose Antonio; Sirakoulis, Georgios; Salvador, Emili; Pedro, Marta; Crespo-Yepes, A.; Martin Martinez, Javier; Rodríguez Martínez, Rosana; Nafría Maqueda, Montserrat (2021-04)
      Article
      Open Access
      Resistive Random Access Memory (ReRAM) is apromising novel memory technology for non-volatile storing, with low-power operation and ultra-high area density. However, ReRAM memories still face issues through commerciali ...
    • Towards the simulation and emulation of large-scale hardware designs 

      López Paradís, Guillem (Universitat Politècnica de Catalunya, 2020-10-29)
      Master thesis
      Open Access
      The heritage of Moore's law has converged in a heterogeneous processor with a many-core and different application- or domain-specific accelerators. Having also finished the benefits of Dennard scaling, we have ended up in ...