Now showing items 1-10 of 10

  • Evaluating the effect of last-level cache sharing on integrated GPU-CPU systems with heterogeneous applications 

    García Flores, Víctor; Gomez Luna, J.; Grass, Thomas Dieter; Rico, Alejandro; Ayguadé Parra, Eduard; Pena, A. J. (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Restricted access - publisher's policy
    Heterogeneous systems are ubiquitous in the field of High- Performance Computing (HPC). Graphics processing units (GPUs) are widely used as accelerators for their enormous computing potential and energy efficiency; ...
  • MUSA: a multi-level simulation approach for next-generation HPC machines 

    Grass, Thomas; Allande, César; Armejach, Adrià; Rico, Alejandro; Ayguadé Parra, Eduard; Labarta, Jesús; Valero Cortés, Mateo; Casas, Marc; Moreto Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Restricted access - publisher's policy
    The complexity of High Performance Computing (HPC) systems is increasing in the number of components and their heterogeneity. Interactions between software and hardware involve many different aspects which are typically ...
  • POSTER: Exploiting asymmetric multi-core processors with flexible system sofware 

    Chronaki, Kallia; Moreto Planas, Miquel; Casas Guix, Marc; Rico, Alejandro; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2016)
    Conference lecture
    Open Access
    Energy efficiency has become the main challenge for high performance computing (HPC). The use of mobile asymmetric multi-core architectures to build future multi-core systems is an approach towards energy savings while ...
  • Rebalancing the core front-end through HPC code analysis 

    Milic, Ugljesa; Carpenter, Paul; Rico, Alejandro; Ramirez, Alex (IEEE, 2016-10-10)
    Conference report
    Open Access
    There is a need to increase performance under the same power and area envelope to achieve Exascale technology in high performance computing (HPC). The today's chip multiprocessor (CMP) design is tailored by traditional ...
  • Rebalancing the core front-end through HPC code analysis 

    Milic, Ugljesa; Carpenter, Paul; Rico, Alejandro; Ramirez, Alex (IEEE, 2016-09-25)
    Conference lecture
    Open Access
    There is a need to increase performance under the same power and area envelope to achieve Exascale technology in high performance computing (HPC). The today's chip multiprocessor (CMP) design is tailored by traditional ...
  • Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications 

    Milic, Ugljesa; Rico, Alejandro; Carpenter, Paul; Ramirez, Alex (Institute of Electrical and Electronics Engineers (IEEE), 2017-07-13)
    Conference lecture
    Open Access
    High performance computing (HPC) applications have parallel code sections that must scale to large numbers of cores, which makes them sensitive to serial regions. Current supercomputing systems with heterogeneous or ...
  • TaskPoint: sampled simulation of task-based programs 

    Grass, Thomas Dieter; Rico, Alejandro; Casas, Marc; Moreto Planas, Miquel; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    Sampled simulation is a mature technique for reducing simulation time of single-threaded programs, but it is not directly applicable to simulation of multi-threaded architectures. Recent multi-threaded sampling techniques ...
  • Task scheduling techniques for asymmetric multi-core systems 

    Chronaki, Kallia; Rico, Alejandro; Casas, Marc; Moreto Planas, Miquel; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2016-11-29)
    Article
    Open Access
    As performance and energy efficiency have become the main challenges for next-generation high-performance computing, asymmetric multi-core architectures can provide solutions to tackle these issues. Parallel programming ...
  • The Mont-Blanc prototype: an alternative approach for high-performance computing systems 

    Rajovic, Nikola; Ramírez Bellido, Alejandro; Rico, Alejandro; Mantovani, Filippo; Ruiz, Daniel; Villarubi, Oriol; Gómez, Constantino; Backes, Luna; Nieto, Diego; Servat, Harald; Martorell Bofill, Xavier; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Adeniyi-Jones, Chris; Derradji, Said; Gloaguen, Hervé; Lanucara, Piero; Sanna, Nico; Mehaut, Jean-François; Pouget, Kevin; Videau, Brice; Boyer, Eric; Allalen, Momme; Auweter, Axel; Brayford, David; Tafani, Daniele; Brömmel, Dirk; Halver, René; Meinke, Jan H.; Beivide Palacio, Ramon; Benito, Mariano; Vallejo, Enrique (2016)
    External research report
    Open Access
    High-performance computing (HPC) is recognized as one of the pillars for further advance of science, industry, medicine, and education. Current HPC systems are being developed to overcome emerging challenges in order to ...
  • The Mont-Blanc prototype: an alternative approach for HPC systems 

    Rajovic, Nikola; Rico, Alejandro; Mantovani, Filippo; Ruiz, Daniel; Vlarrubi, Josep O.; Gomez, Constantino; Backes, Luna; Nieto, Diego; Servat, Harald; Martorell Bofill, Xavier; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Adeniyi-Jones, Chris; Derradji, Said; Gloaguen, Hervé; Lanucara, Piero; Sanna, Nico; Mehaut, Jean-François; Pouget, Kevin; Videau, Brice; Boyer, Eric; Allalen, Momme; Auweter, Axel; Brayford, David; Tafani, Daniele; Weinberg, Volker; Brömmel, Dirk; Halver, René; Meinke, Jan H.; Beivide Palacio, Ramon; Benito, Mariano; Vallejo, Enrique; Valero Cortés, Mateo; Ramirez, Alex (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    High-performance computing (HPC) is recognized as one of the pillars for further progress in science, industry, medicine, and education. Current HPC systems are being developed to overcome emerging architectural challenges ...