Now showing items 1-4 of 4

  • A distributed processor state management architecture for large-window processors 

    González, Isidro; Galluzzi, Marco; Veidenbaum, Alexander V.; Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Conference report
    Open Access
    Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed architectures replace a re-order buffer (ROB) with ...
  • A novel architecture for large windows processors 

    González, Isidro; Galluzzi, Marco; Veidenbaum, Alex; Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2007-11)
    External research report
    Open Access
    Several processor architectures with large instruction windows have been proposed. They improve performance by maintaining hundreds of instructions in flight to increase the level of instruction parallelism (ILP). Such ...
  • Direct instruction wakeup for out-of-order processors 

    Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Veidenbaum, Alex; Villa, Luis A; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    Instruction queues consume a significant amount of power in high-performance processors, primarily due to instruction wakeup logic access to the queue structures. The wakeup logic delay is also a critical timing parameter. ...
  • The MS-processor's register file timing and power evaluation 

    Gonzalez Martin, Isidro; Cristal Kestelman, Adrián; Veindenbaum, Alex; Ramírez, Marco Antonio; Valero Cortés, Mateo (2008-09)
    External research report
    Open Access
    Power evaluation is an important issue in new proposal chip level architectures due to the big amount of power is dissipated as head and chips have limited head dissipation capacity. The evaluation shown in this technical ...