Browsing by Author "Radojkovic, Petar"
Now showing items 1-19 of 19
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Another trip to the wall: how much will stacked DRAM benefit HPC?
(Association for Computing Machinery (ACM), 2015)
Conference report
Restricted access - publisher's policyFirst defined two decades ago, the memory wall remains a fundamental limitation to system performance. Recent innovations in 3D-stacking technology enable DRAM devices with much higher bandwidths than traditional DIMMs. ... -
Characterizing the resource-sharing levels of the UltraSparc T2 processor
(Association for Computing Machinery (ACM), 2009)
Conference report
Restricted access - publisher's policyThread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or ... -
Energy efficient HPC on embedded SoCs : optimization techniques for mali GPU
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Restricted access - publisher's policyA lot of effort from academia and industry has been invested in exploring the suitability of low-power embedded technologies for HPC. Although state-of-the-art embedded systems-on-chip (SoCs) inherently contain GPUs that ... -
HPC benchmarking: scaling right and looking beyond the average
(Springer, 2018)
Conference report
Open AccessDesigning a balanced HPC system requires an understanding of the dominant performance bottlenecks. There is as yet no well established methodology for a unified evaluation of HPC systems and workloads that quantifies the ... -
Large-memory nodes for energy efficient high-performance computing
(Association for Computing Machinery (ACM), 2016)
Conference report
Open AccessEnergy consumption is by far the most important contributor to HPC cluster operational costs, and it accounts for a significant share of the total cost of ownership. Advanced energy-saving techniques in HPC components have ... -
Main memory in HPC: do we need more, or could we live with less?
(2017-03)
Article
Open AccessAn important aspect of High-Performance Computing (HPC) system design is the choice of main memory capacity. This choice becomes increasingly important now that 3D-stacked memories are entering the market. Compared with ... -
Measuring operating system overhead on CMT processors
(IEEE Computer Society Publications, 2008)
Conference report
Open AccessNumerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing ... -
Measuring operating system overhead on Sun UltraSparc T1 processor
(2009-06)
Conference report
Open AccessNumerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing, ... -
Overhead of the spin-lock loop in UltraSPARC T2
(2008-06-04)
Conference report
Open AccessSpin locks are task synchronization mechanism used to provide mutual exclusion to shared software resources. Spin locks have a good performance in several situations over other synchronization mechanisms, i.e., when on ... -
Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach
(IEEE, 2017-09-28)
Conference lecture
Open AccessPower consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able ... -
Performance impact of a slower main memory: a case study of STT-MRAM in HPC
(Barcelona Supercomputing Center, 2017-05-04)
Conference report
Open AccessMemory systems are major contributors to the deployment and operational costs of large-scale HPC clusters [1][2][3], as well as one of the most important design parameters that significantly affect system performance. In ... -
Performance impact of a slower main memory: a case study of STT-MRAM in HPC
(ACM, 2016-10)
Conference lecture
Open AccessIn high-performance computing (HPC), significant effort is invested in research and development of novel memory technologies. One of them is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) --- byte-addressable, ... -
PROFET: modeling system performance and energy without simulating the CPU
(2019-06)
Article
Open AccessThe approaching end of DRAM scaling and expansion of emerging memory technologies is motivating a lot of research in future memory systems. Novel memory systems are typically explored by hardware simulators that are slow ... -
Thread assignment in multicore/multithreaded processors: A statistical approach
(2016-01-01)
Article
Open AccessThe introduction of multicore/multithreaded processors, comprised of a large number of hardware contexts (virtual CPUs) that share resources at multiple levels, has made process scheduling, in particular assignment of ... -
Thread assignment of multithreaded network applications in multicore/multithreaded processors
(2013-12)
Article
Open AccessThe introduction of multithreaded processors comprised of a large number of cores with many shared resources makes thread scheduling, and in particular optimal assignment of running threads to processor hardware contexts ... -
Thread to strand binding of parallel network applications in massive multi-threaded systems
(2010-05)
Article
Restricted access - publisher's policyIn processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a single level of resource sharing, such as pure-SMT ... -
Thread to strand binding of parallel network applications in massive multi-threaded systems
(ACM Press. Association for Computing Machinery, 2010-01)
Conference report
Restricted access - publisher's policyIn processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a single level of resource sharing, such as pure-SMT ... -
Understanding the overhead of the spin-lock loop in CMT architectures
(2008)
Conference report
Open AccessSpin locks are a synchronization mechanisms used to provide mutual exclusion to shared software resources. Spin locks are used over other synchronization mechanisms in several situations, like when the average waiting ... -
Understanding the overhead of the spin-lock loop in CMT architectures
(2008)
Conference report
Open AccessAbstract—Spin locks are a synchronization mechanisms used to provide mutual exclusion to shared software resources. Spin locks are used over other synchronization mechanisms in several situations, like when the average ...
