Browsing by Subject "RISC microprocessors"
Now showing items 1-18 of 18
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Benchmarking vector accelerators with an automotive application
(Universitat Politècnica de Catalunya, 2023-06-29)
Master thesis
Open AccessThis project focuses on the development and optimization of an automotive radar application.The project aims to generate a functional version of the application in collaboration with Infineon Germany. The implementation ... -
Design under test interface implementation and stimulus in the verification of a RISC-V vector accelerator
(Universitat Politècnica de Catalunya, 2021)
Master thesis
Restricted access - author's decision
Covenantee: Barcelona Supercomputing CenterThe production of a microprocessor is one of the most complex and expensive processes in the industry these days. These high costs are why big companies dedicate most of their efforts to design verification during the ... -
Design, implementation and evaluation of post-quantum cryptography accelerators in 22nm FDSOI technology
(Universitat Politècnica de Catalunya, 2023-02-02)
Master thesis
Open AccessThis thesis aims to design and implement a Post-Quantum Cryptographic (PQC) algorithm accelerator to integrate it inside a System On Chip (SoC) for FPGA and ASIC targets. The accelerated PQC algorithm is called CRYSTALS-Kyber, ... -
Disseny d'un microprocessador en una FPGA basat en màquines algorítmiques
(Universitat Politècnica de Catalunya, 2023-07-12)
Bachelor thesis
Open AccessEn el present projecte es proposa desenvolupar un processador a través de la metodologia de màquines algorítmiques. Posteriorment, s’implementa en una FPGA per validar el funcionament del disseny. L’arquitectura del set ... -
Extending a modern RISC-V vector accelerator with direct access to the memory hierarchy through AMBA 5 CHI.
(Universitat Politècnica de Catalunya, 2022-01-26)
Bachelor thesis
Open Access
Covenantee: Barcelona Supercomputing CenterEl BSC està desenvolupant un accelerador vectorial desacoblat basat en RISC-V. A la versió anterior d'aquest projecte, l'accelerador utilitza Open Vector Interface (OVI) per accedir a la memòria cache L2 compartida, a ... -
Extension and improvement of a PCIe-based FPGA environment for testing HPC architectures
(Universitat Politècnica de Catalunya, 2023-06-29)
Master thesis
Open AccessThe European Processor Initiative (EPI) is a European project that performs research to advance High-Performance Computing (HPC) through the development of European technology. EPI aims at the development of a general-purpose ... -
Hypervisor extension in a RISC-V processor
(Universitat Politècnica de Catalunya, 2023-05-15)
Master thesis
Open AccessEls entorns virtualitzats s'utilitzen habitualment en la majoria d'aplicacions com ara telèfons mòbils, serveis al núvol, superordinadors i molt més. L'ús d'entorns virtuals permet múltiples contextos virtualitzats aïllats ... -
Implementation feasibility of an integrated LPDDR4 PHY block
(Universitat Politècnica de Catalunya, 2022-06)
Master thesis
Open AccessOne of the bottlenecks in the performance of academic RISC-V ASIC processors is high-speed memory access. The use of high speed DDR RAM chips on the board requires the integration in the ASIC of a very complex physical ... -
Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems
(Universitat Politècnica de Catalunya, 2023-10-20)
Master thesis
Open AccessIn Hard Real-time Systems, the execution of tasks must be completed within a certain timeframe, known as deadline. In consequence, when a hard-real time system is designed, it is strictly necessary to assume that its tasks ... -
Infrastructure and functional correctness in the verification of a RISC-V vector accelerator
(Universitat Politècnica de Catalunya, 2022-01-26)
Master thesis
Restricted access - author's decision
Covenantee: Barcelona Supercomputing CenterWhen we talk about hardware development, many efforts are made to tape out a bug-free design. The hardware fabrication process costs enormous amounts of money to the companies, so they can not afford to produce faulty ... -
Integration of a High Performance Cache with a RISC-V Core and Cost-Benefit Analysis
(Universitat Politècnica de Catalunya, 2023-10-31)
Master thesis
Open AccessIt is widely known that memory operations have the highest latency in modern processors. Because of the high usage of these operations in many types of programs, it is crucial for a system to effectively tolerate this ... -
Movement of vector elements inside a de-coupled vector processing unit for high-performance memory operations
(Universitat Politècnica de Catalunya, 2023-01-24)
Bachelor thesis
Open Access
Covenantee: Barcelona Supercomputing CenterThis thesis is part of the eProcessor project. Within it, the BSC is developing a RISC-V based decoupled vector accelerator. This accelerator must support the execution of vector memory instructions. More specifically, I ... -
Performance Analysis of Rainbow on ARM Cortex-M4
(Universitat Politècnica de Catalunya, 2019-07-30)
Bachelor thesis
Open AccessThe risk posed by a fully operational quantum computer has anticipated a revolution in the way to approach the level of security provided by a cryptographic algorithm. Public keybased solutions such as RSA or ECC will be ... -
Performance testing of ML and HDC : parallelized applications on top of RISC-V architecture
(Universitat Politècnica de Catalunya, 2022-06-28)
Master thesis
Open AccessThe economic impact that proprietary ISA has on the market increased the interest in using Open Source ISA. More specifically RISC-V has been getting a lot of traction in the research community. The Open Source environment ... -
RTL design and implementation of a framebuffer for a RISC-V processor
(Universitat Politècnica de Catalunya, 2020-10-28)
Bachelor thesis
Open Access
Covenantee: Barcelona Supercomputing CenterEl conjunt d'instruccions o ISA (de l'anglès instruction set architecture) RISC-V i la fundació que el recolza segueixen creixent ràpidament com una alternativa open-source per als dissenys hardware. Tot i que el software ... -
Study of a CFD application on RISC-V core with a wide vector unit
(Universitat Politècnica de Catalunya, 2023-06-29)
Bachelor thesis
Open AccessL'European Processor Initiative (EPI) és un projecte europeu que realitza investigacions per avançar en la computació d'alt rendiment (HPC) mitjançant el desenvolupament de tecnologia europea. EPI té com a objectiu ... -
Testbench development and performance bottleneck analysis of the cache coherence protocols in multiprocessor systems based on the RISC-V Lagarto architecture
(Universitat Politècnica de Catalunya, 2022-04-26)
Master thesis
Open AccessThe Lagarto project constitutes the basis of some important processor designs; some tapeouts with different versions and refactors have been done by collaboration. The first integration of the processor has been done using ... -
Verilog implementation of a low-cost vector AI accelerator and integration in a RISC-V processor
(Universitat Politècnica de Catalunya, 2023-01-24)
Bachelor thesis
Open Access
Covenantee: Barcelona Supercomputing CenterEl acelerador SPARROW AI portátil y de bajo costo se propuso y demostró recientemente en VHDL en dos procesadores espaciales, el LEON3 y el NOEL-V. En este trabajo de fin de grado se implementa SPARROW en SystemVerilog y ...
