Browsing by Subject "RISC (Microprocessadors)"

Now showing items 1-12 of 12

    • Benchmarking vector accelerators with an automotive application 

      Petrovic, Matej (Universitat Politècnica de Catalunya, 2023-06-29)
      Master thesis
      Open Access
      This project focuses on the development and optimization of an automotive radar application.The project aims to generate a functional version of the application in collaboration with Infineon Germany. The implementation ...

    • Design under test interface implementation and stimulus in the verification of a RISC-V vector accelerator 

      Jiménez Arador, Víctor (Universitat Politècnica de Catalunya, 2021)
      Master thesis
      Restricted access - author's decision
      Covenantee:   Barcelona Supercomputing Center
      The production of a microprocessor is one of the most complex and expensive processes in the industry these days. These high costs are why big companies dedicate most of their efforts to design verification during the ...

    • Design, implementation and evaluation of post-quantum cryptography accelerators in 22nm FDSOI technology 

      Carril Gil, Xavier (Universitat Politècnica de Catalunya, 2023-02-02)
      Master thesis
      Open Access
      This thesis aims to design and implement a Post-Quantum Cryptographic (PQC) algorithm accelerator to integrate it inside a System On Chip (SoC) for FPGA and ASIC targets. The accelerated PQC algorithm is called CRYSTALS-Kyber, ...

    • Extending a modern RISC-V vector accelerator with direct access to the memory hierarchy through AMBA 5 CHI. 

      Roset Julia, Miquel (Universitat Politècnica de Catalunya, 2022-01-26)
      Bachelor thesis
      Open Access
      Covenantee:   Barcelona Supercomputing Center
      El BSC està desenvolupant un accelerador vectorial desacoblat basat en RISC-V. A la versió anterior d'aquest projecte, l'accelerador utilitza Open Vector Interface (OVI) per accedir a la memòria cache L2 compartida, a ...

    • Extension and improvement of a PCIe-based FPGA environment for testing HPC architectures 

      Querol De Porras, Andrea (Universitat Politècnica de Catalunya, 2023-06-29)
      Master thesis
      Open Access
      The European Processor Initiative (EPI) is a European project that performs research to advance High-Performance Computing (HPC) through the development of European technology. EPI aims at the development of a general-purpose ...

    • Hypervisor extension in a RISC-V processor 

      Gauchola Vilardell, Jaume (Universitat Politècnica de Catalunya, 2023-05-15)
      Master thesis
      Open Access
      Els entorns virtualitzats s'utilitzen habitualment en la majoria d'aplicacions com ara telèfons mòbils, serveis al núvol, superordinadors i molt més. L'ús d'entorns virtuals permet múltiples contextos virtualitzats aïllats ...

    • Implementation feasibility of an integrated LPDDR4 PHY block 

      Codina i Vilanova, Pol (Universitat Politècnica de Catalunya, 2022-06)
      Master thesis
      Open Access
      One of the bottlenecks in the performance of academic RISC-V ASIC processors is high-speed memory access. The use of high speed DDR RAM chips on the board requires the integration in the ASIC of a very complex physical ...

    • Improving the Front-end Performance of a Time Randomised Processor for Hard Real-Time Systems 

      Rufart Blasco, Eric (Universitat Politècnica de Catalunya, 2023-10-20)
      Master thesis
      Open Access
      In Hard Real-time Systems, the execution of tasks must be completed within a certain timeframe, known as deadline. In consequence, when a hard-real time system is designed, it is strictly necessary to assume that its tasks ...

    • Movement of vector elements inside a de-coupled vector processing unit for high-performance memory operations 

      Aguilera Dangla, Albert (Universitat Politècnica de Catalunya, 2023-01-24)
      Bachelor thesis
      Open Access
      Covenantee:   Barcelona Supercomputing Center
      This thesis is part of the eProcessor project. Within it, the BSC is developing a RISC-V based decoupled vector accelerator. This accelerator must support the execution of vector memory instructions. More specifically, I ...

    • Performance Analysis of Rainbow on ARM Cortex-M4 

      Moya Riera, Joan (Universitat Politècnica de Catalunya, 2019-07-30)
      Bachelor thesis
      Open Access
      The risk posed by a fully operational quantum computer has anticipated a revolution in the way to approach the level of security provided by a cryptographic algorithm. Public keybased solutions such as RSA or ECC will be ...

    • Performance testing of ML and HDC : parallelized applications on top of RISC-V architecture 

      Vergés Boncompte, Pere (Universitat Politècnica de Catalunya, 2022-06-28)
      Master thesis
      Open Access
      The economic impact that proprietary ISA has on the market increased the interest in using Open Source ISA. More specifically RISC-V has been getting a lot of traction in the research community. The Open Source environment ...

    • RTL design and implementation of a framebuffer for a RISC-V processor 

      Rodas Quiroga, Narcís (Universitat Politècnica de Catalunya, 2020-10-28)
      Bachelor thesis
      Open Access
      Covenantee:   Barcelona Supercomputing Center
      El conjunt d'instruccions o ISA (de l'anglès instruction set architecture) RISC-V i la fundació que el recolza segueixen creixent ràpidament com una alternativa open-source per als dissenys hardware. Tot i que el software ...