Browsing by Author "Quiroga Esparza, Josué Vladimir"
Now showing items 1-3 of 3
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Functional verification of a RISC-V vector accelerator
(Institute of Electrical and Electronics Engineers (IEEE), 2023-06)
Article
Open AccessWe present the functional verification efforts for an academic RISC-V based vector accelerator, successfully taped-out in the context of the European Processor Initiative. For our novel RISC-V based decoupled vector ... -
Heterogeneous CPU/GPU Memory Hierarchy Analysis and Optimization
(Universitat Politècnica de Catalunya, 2015-07)
Master thesis
Open AccessIn this master thesis, we propose a scheduling reordering for heterogeneous processors based on a hysteresis detector to give some fairness and speedup to the memory request threads taking advantage of the bank level ... -
Vitruvius+: An area-efficient RISC-V decoupled vector coprocessor for high performance computing applications
(2023-03-01)
Article
Open AccessThe maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores ...
