Browsing by Author "Quiñones, Eduardo"
Now showing items 1-20 of 61
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A cache design for probabilistically analysable real-time systems
(2013)
Conference report
Restricted access - publisher's policyCaches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. ... -
A confidence assessment of WCET estimates for software time randomized caches
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessObtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates ... -
A Functional Safety OpenMP∗ for Critical Real-Time Embedded Systems
(Springer, 2017-08-17)
Part of book or chapter of book
Open AccessOpenMP* has recently gained attention in the embedded domain by virtue of the augmentations implemented in the last specification. Yet, the language has a minimal impact in the embedded real-time domain mostly due to the ... -
A static scheduling approach to enable safety-critical OpenMP applications
(IEEE, 2017-02-20)
Conference report
Open AccessParallel computation is fundamental to satisfy the performance requirements of advanced safety-critical systems. OpenMP is a good candidate to exploit the performance opportunities of parallel platforms. However, safety-critical ... -
Achieving timing composability with measurement-based probabilistic timing analysis
(2013)
Conference report
Restricted access - publisher's policyProbabilistic Timing Analysis (PTA) allows complex hardware acceleration features, which defeat classic timing analysis, to be used in hard real-time systems. PTA can do that because it drastically reduces intrinsic ... -
Adapting TDMA arbitration for measurement-based probabilistic timing analysis
(Elsevier, 2017-07)
Article
Open AccessCritical Real-Time Embedded Systems require functional and timing validation to prove that they will perform their functionalities correctly and in time. For timing validation, a bound to the Worst-Case Execution Time ... -
Adaptive optics control with reinforcement learning: first steps
(Barcelona Supercomputing Center, 2021-05)
Conference report
Open AccessWhen planar wavefronts from distant stars traverse the atmosphere, they become distorted due to the atmosphere’s inhomogeneous temperature distribution. Adaptive Optics (AO) is the field in charge of correcting those ... -
An Analysis of Lazy and Eager Limited Preemption Approaches under DAG-Based Global Fixed Priority Scheduling
(Institute of Electrical and Electronics Engineers (IEEE), 2017-07-03)
Conference lecture
Open AccessDAG-based scheduling models have been shown to effectively express the parallel execution of current many-core heterogeneous architectures. However, their applicability to real-time settings is limited by the difficulties ... -
An analyzable memory controller for hard real-time CMPs
(2010-02-05)
Article
Open AccessMulticore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences ... -
An ILP-based real-time scheduler for distributed and heterogeneous computing environments
(Barcelona Supercomputing Center, 2019-05-07)
Conference report
Open Access -
Applying measurement-based probabilistic timing analysis to buffer resources
(2013)
Conference report
Open AccessThe use of complex hardware makes it difficult for current timing analysis techniques to compute trustworthy and tight worst-case execution time (WCET) bounds. Those techniques require detailed knowledge of the internal ... -
Big Data Analytics for Smart Cities: The H2020 CLASS Project
(ACM, 2018-06-04)
Conference lecture
Open AccessApplying big-data technologies to field applications has resulted in several new needs. First, processing data across a compute continuum spanning from cloud to edge to devices, with varying capacity, architecture etc. ... -
Bus designs for time-probabilistic multicore processors
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Conference report
Restricted access - publisher's policyProbabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ... -
Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration
(Institute of Electrical and Electronics Engineers (IEEE), 2016-10-11)
Article
Open AccessNumerous researchers have studied the contention that arises among tasks running in parallel on a multicore processor. Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which ... -
Containing timing-related certification cost in automotive systems deploying complex hardware
(Association for Computing Machinery (ACM), 2014)
Conference report
Restricted access - publisher's policyMeasurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the ... -
Contention in multicore hardware shared resources: Understanding of the state of the art
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2014)
Conference report
Open AccessThe real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been ... -
Data bus slicing for contention-free multicore real-time memory systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessMemory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ... -
Deconstructing bus access control policies for real-time multicores
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Conference report
Restricted access - publisher's policyMulticores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ... -
DTM: degraded test mode for fault-aware probabilistic timing analysis
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Conference report
Restricted access - publisher's policyExisting timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current ... -
Early register release for out-of-order processors with register windows
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Conference report
Open AccessRegister windows is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register ...
