Browsing by Author "Pleiter, Dirk"

Now showing items 1-3 of 3

    • Mainstream vs. emerging HPC: metrics, trade-offs and lessons learned 

      Radulović, Milan; Asifuzzaman, Kazi; Živanovič, Darko; Rajovic, Nikola; Colin de Verdiére, Guillaume; Pleiter, Dirk; Marazakis, Manolis; Kallimanis, Nikolaos; Carpenter, Paul Matthew; Radojković, Petar; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Conference report
      Open Access
      Various servers with different characteristics and architectures are hitting the market, and their evaluation and comparison in terms of HPC features is complex and multidimensional. In this paper, we share our experience ...

    • Mont-Blanc 2020: Towards scalable and power efficient European HPC processors 

      Armejach Sanosa, Adrià; Brank, Bine; Cortina Guardia, Jordi; Dolique, François; Hayes, Timothy; Ho, Nam; Lagadec, Pierre-Axel; Lemaire, Romain; López Paradís, Guillem; Marliac, Laurent; Moretó Planas, Miquel; Marcuello Pascual, Pedro; Pleiter, Dirk; Tan, Xubin; Derradji, Said (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      The Mont-Blanc 2020 (MB2020) project has triggered the development of the next generation industrial processor for Big Data and High Performance Computing (HPC). MB2020 is paving the way to the future low-power European ...

    • Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach 

      Rigo, Alvise; Pinto, Christian; Pouget, Kevin; Raho, Daniel; Dutoit, Denis; Martinez, Pierre-Yves; Doran, Chris; Benini, Luca; Mavroidis, Iakovos; Marazakis, Manolis; Bartsch, Valeria; Lonsdale, Guy; Pop, Antoniu; Goodacre, John; Colliot, Annaïk; Carpenter, Paul Matthew; Radojković, Petar; Pleiter, Dirk; Drouin, Dominique; Dupont de Dinechin, Benoît (IEEE, 2017-09-28)
      Conference lecture
      Open Access
      Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able ...