Now showing items 1-5 of 5

    • Data placement in HPC architectures with heterogeneous off-chip memory 

      Pavlovic, Milan; Puzovic, Nikola; Ramírez Bellido, Alejandro (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Conference report
      Open Access
      The performance of HPC applications is often bounded by the underlying memory system's performance. The trend of increasing the number of cores on a chip imposes even higher memory bandwidth and capacity requirements. The ...
    • Main memory in HPC: do we need more, or could we live with less? 

      Živanovič, Darko; Pavlovic, Milan; Radulovic, Milan; Shin, Hyunsung; Son, Jongpil; McKee, Sally A.; Carpenter, Paul M.; Radojkovic, Petar; Ayguadé Parra, Eduard (2017-03)
      Article
      Open Access
      An important aspect of High-Performance Computing (HPC) system design is the choice of main memory capacity. This choice becomes increasingly important now that 3D-stacked memories are entering the market. Compared with ...
    • On the simulation of large-scale architectures using multiple application abstraction levels 

      Rico Carro, Alejandro; Cabarcas, Felipe; Villavieja Prados, Carlos; Pavlovic, Milan; Vega, Augusto; Etsion, Yoav; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2012-01-23)
      Article
      Restricted access - publisher's policy
      Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not ...
    • Performance impact of a slower main memory: a case study of STT-MRAM in HPC 

      Asifuzzaman, Kazi; Pavlovic, Milan; Radulovic, Milan; Zaragoza, David; Kwon, Ohseong; Ryoo, Kyung-Chang; Radojkovic, Petar (ACM, 2016-10)
      Conference lecture
      Open Access
      In high-performance computing (HPC), significant effort is invested in research and development of novel memory technologies. One of them is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) --- byte-addressable, ...
    • Performance impact of a slower main memory: a case study of STT-MRAM in HPC 

      Asifuzzaman, Kazi; Pavlovic, Milan; Radulovic, Milan; Zaragoza, David; Kwon, Ohseong; Ryoo, Kyung-Chang; Radojkovic, Petar (Barcelona Supercomputing Center, 2017-05-04)
      Conference report
      Open Access
      Memory systems are major contributors to the deployment and operational costs of large-scale HPC clusters [1][2][3], as well as one of the most important design parameters that significantly affect system performance. In ...