Now showing items 1-18 of 18

  • An hybrid eDRAM/SRAM macrocell to implement first-level data caches 

    Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Lorente, Vicente; Canal Corretger, Ramon; López, Pedro; Duato, José (Association for Computing Machinery (ACM), 2009)
    Conference report
    Restricted access - publisher's policy
    SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are ...
  • Conflict-free strides for vectors in matched memories 

    Valero Cortés, Mateo; Lang, Tomas; Llaberia Griñó, José M.; Peiron Guàrdia, Montse; Navarro Guerrero, Juan José; Ayguadé Parra, Eduard (1991-12)
    Article
    Open Access
    Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access to one family of strides in vector processors with matched memories. The paper extends these ...
  • Cost-effective compiler directed memory prefetching and bypassing 

    Ortega Fernández, Daniel; Ayguadé Parra, Eduard; Baer, Jean-Loup; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Conference report
    Open Access
    Ever increasing memory latencies and deeper pipelines push memory farther from the processor. Prefetching techniques aim is to bridge these two gaps by fetching data in advance to both the L1 cache and the register file. ...
  • CRAID: Online RAID upgrades using dynamic hot data reorganization 

    Miranda Bueno, Alberto; Cortés, Toni (USENIX Association, 2014)
    Conference report
    Open Access
    Current algorithms used to upgrade RAID arrays typically require large amounts of data to be migrated, even those that move only the minimum amount of data required to keep a balanced data load. This paper presents CRAID, ...
  • Distributing orthogonal redundancy on adaptive disk arrays 

    González, José Luis; Cortés, Toni (Springer, 2008)
    Conference report
    Restricted access - publisher's policy
    When upgrading storage systems, the key is migrating data from old storage subsystems to the new ones for achieving a data layout able to deliver high performance I/O, increased capacity and strong data availability while ...
  • ECHOFS: a scheduler-guided temporary filesystem to leverage node-local NVMS 

    Miranda, Alberto; Nou Castell, Ramon; Cortés, Toni (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    The growth in data-intensive scientific applications poses strong demands on the HPC storage subsystem, as data needs to be copied from compute nodes to I/O nodes and vice versa for jobs to run. The emerging trend of adding ...
  • Freezing Time: a new approach for emulating fast storage devices using VM 

    Bona, Luis C.E.; Elias, Alessandro; Ziviani, Andre P.; Cortés, Toni; Nou Castell, Ramon; Alves, Marco A.Z. (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    Recently we are seeing a considerable effort from both academy and industry in proposing new technologies for storage devices. Often these devices are not readily available for evaluation and methods to allow performing ...
  • HetFS: A heterogeneous file system for everyone 

    Koloventzos, Georgios; Nou Castell, Ramon; Miranda, Alberto; Cortés, Toni (Springer, 2017)
    Conference report
    Open Access
    Storage devices have been getting more and more diverse during the last decade. The advent of SSDs made it painfully clear that rotating devices, such as HDDs or magnetic tapes, were lacking in regards to response time. ...
  • Implementació en HDL d'un arbre binari de cerca auto-balancejat 

    Mercadé Ibáñez, Àlvar (Universitat Politècnica de Catalunya, 2017-06-27)
    Master thesis (pre-Bologna period)
    Open Access
    Covenantee:  Barcelona Supercomputing Centre
    Amb la proliferació de les arquitectures multi-core i many-core, s’han emprat molts esforços en l’especificació i la implementació de nous models de programació, que facilitessin als desenvolupadors de programari la ...
  • Increasing the number of strides for conflict-free vector access 

    Valero Cortés, Mateo; Lang, Tomas; Llaberia Griñó, José M.; Peiron Guàrdia, Montse; Ayguadé Parra, Eduard; Navarro Guerrero, Juan José (1992-05)
    Article
    Open Access
    Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we ...
  • ITCA: Inter-Task Conflict-Aware CPU accounting for CMP 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Valero Cortés, Mateo (2010)
    Conference report
    Open Access
    Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...
  • Light NUCA: a proposal for bridging the inter-cache latency gap 

    Suárez, Dario; Monreal Arnal, Teresa; Vallejo, Fernando; Beivide Palacio, Julio Ramón; Viñals Yufera, Víctor (IEEE Computer Society, 2009)
    Conference lecture
    Open Access
    To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). ...
  • Memorias SRAM en "Hardware Description Language (HDL)" para una plataforma de simulación de codigos en HDL. 

    Bartra Carreras, Oscar (Universitat Politècnica de Catalunya, 2010-04-16)
    Bachelor thesis
    Open Access
  • Memory Dependence Prediction Methods Study and Improvement Proposals 

    Pflücker López, Otto Fernando (Universitat Politècnica de Catalunya, 2011-03-28)
    Master thesis
    Open Access
    English: Nowadays, most modern high performance processors employ out-of-order (O3) execution. In these processors, instructions are executed as soon as possible increasing in this way the instruction level parallelism ...
  • Performance impacts with reliable parallel file systems at exascale level 

    Nou Castell, Ramon; Miranda, Alberto; Cortés, Toni (Springer, 2015)
    Conference report
    Restricted access - publisher's policy
    The introduction of Exascale storage into production systems will lead to an increase on the number of storage servers needed by parallel file systems. In this scenario, parallel file system designers should move from the ...
  • Reducing fetch architecture complexity using procedure inlining 

    Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    Fetch engine performance is seriously limited by the branch prediction table access latency. This fact has lead to the development of hardware mechanisms, like prediction overriding, aimed to tolerate this latency. However, ...
  • Sesquickselect: One and a half pivots for cache-efficient selection 

    Martínez Parra, Conrado; Nebel, Markus; Wild, Sebastian (Curran, 2019)
    Conference report
    Open Access
    Because of unmatched improvements in CPU performance, memory transfers have become a bottleneck of program execution. As discovered in recent years, this also affects sorting in internal memory. Since partitioning around ...
  • TM-dietlibc: A TM-aware real-world system library 

    Smiljkovic, Vesna; Nowack, Martin; Miletic, Nebojša; Harris, Tim; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    The simplicity of concurrent programming with Transactional Memory (TM) and its recent implementation in mainstream processors greatly motivates researchers and industry to investigate this field and propose new implementations ...