Now showing items 1-20 of 28

  • Advances in the Hierarchical Emergent Behaviors (HEB) approach to autonomous vehicles 

    Roca, Damian; Milito, Rodolfo; Nemirovsky, Mario; Valero Cortés, Mateo (2018-11-13)
    Article
    Open Access
    Widespread deployment of autonomous vehicles (AVs) presents formidable challenges in terms on handling scalability and complexity, particularly regarding vehicular reaction in the face of unforeseen corner cases. Hierarchical ...
  • A general guide to applying machine learning to computer architecture 

    Nemirovsky, Daniel; Arkose, Tugberk; Markovic, Nikola; Nemirovsky, Mario; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2018)
    Article
    Open Access
    The resurgence of machine learning since the late 1990s has been enabled by significant advances in computing performance and the growth of big data. The ability of these algorithms to detect complex patterns in data which ...
  • An abstraction methodology for the evaluation of multi-core multi-threaded architectures 

    Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (IEEE Computer Society Publications, 2011)
    Conference report
    Restricted access - publisher's policy
    As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to ...
  • Area and laser power scalability analysis in photonic networks-on-chip 

    Abadal Cavallé, Sergi; Cabellos Aparicio, Alberto; Lázaro Villa, José Antonio; Nemirovsky, Mario; Alarcón Cot, Eduardo José; Solé Pareta, Josep (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference lecture
    Restricted access - publisher's policy
    In the last decade, the field of microprocessor architecture has seen the rise of multicore processors, which consist of the interconnection of a set of independent processing units or cores in the same chip. As the number ...
  • Broadcast-enabled massive multicore architectures: a wireless RF approach 

    Abadal Cavallé, Sergi; Sheinman, Benny; Katz, Oded; Markish, Ofer; Elad, Danny; Fournier, Yvan; Roca, Damian; Hanzich, Mauricio; Houzeaux, Guillaume; Nemirovsky, Mario; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2015-09)
    Article
    Open Access
    Broadcast traditionally has been regarded as a prohibitive communication transaction in multiprocessor environments. Nowadays, such a constraint largely drives the design of architectures and algorithms all-pervasive in ...
  • Characterizing the resource-sharing levels of the UltraSparc T2 processor 

    Cakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2009)
    Conference report
    Restricted access - publisher's policy
    Thread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or ...
  • Disaggregated Computing. An Evaluation of Current Trends for Datacentres 

    Meyer, Hugo; Sancho, Jose C.; Quiroga, Josue V.; Zyulkyarov, Ferad; Roca, Damian; Nemirovsky, Mario (Elsevier, 2017)
    Article
    Open Access
    Next generation data centers will likely be based on the emerging paradigm of disaggregated function-blocks-as-a-unit departing from the current state of mainboard-as-a-unit. Multiple functional blocks or bricks such as ...
  • Emergent behaviors in the Internet of things: The ultimate ultra-large-scale system 

    Roca, Damian; Nemirovsky, Daniel; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (2016-11)
    Article
    Open Access
    To reach its potential, the Internet of Things (IoT) must break down the silos that limit applications' interoperability and hinder their manageability. Doing so leads to the building of ultra-large-scale systems (ULSS) ...
  • Fog function virtualization: A flexible solution for IoT applications 

    Roca, Damian; Quiroga, Josue V.; Valero Cortés, Mateo; Nemirovsky, Mario (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Conference report
    Open Access
    The Internet of Things applications must carefully assess certain crucial factors such as the real-time and largely distributed nature of the “things”. Fog Computing provides an architecture to satisfy those requirements ...
  • Graphene-enabled wireless communication for massive multicore architectures 

    Abadal Cavallé, Sergi; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto; Lemme, Max; Nemirovsky, Mario (2013-11-11)
    Article
    Restricted access - publisher's policy
    Current trends in microprocessor architecture design are leading towards a dramatic increase of core-level parallelization, wherein a given number of independent processors or cores are interconnected. Since the main ...
  • Improving the energy efficiency of hardware-assisted watchpoint systems 

    Karakostas, Vasileios; Tomić, Saša; Unsal, Osman Sabri; Nemirovsky, Mario; Cristal Kestelman, Adrián (2013)
    Conference report
    Restricted access - publisher's policy
    Hardware-assisted watchpoint systems enhance the execution of numerous dynamic software techniques, such as memory protection, module isolation, deterministic execution, and data race detection. In this paper, we show ...
  • Internet traffic and the behavior of processing workloads 

    Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Valero Cortés, Mateo (2009-06)
    Conference report
    Open Access
    Nowadays, the evolution of network services provided at the edge of Internet increases the requirements of network applications. Such applications result in complexities thus, the processors need to execute more complex ...
  • iQ: an efficient and flexible queue-based simulation framework 

    Roca, Damian; Nemirovsky, Daniel; Casas, Marc; Moreto Planas, Miquel; Valero Cortés, Mateo; Nemirovsky, Mario (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Conference report
    Open Access
    Conventional system simulators are readily used by computer architects to design and evaluate their processor designs. These simulators provide reasonable levels of accuracy and execution detail but suffer from long ...
  • Measuring operating system overhead on CMT processors 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (IEEE Computer Society Publications, 2008)
    Conference report
    Open Access
    Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing ...
  • Measuring operating system overhead on Sun UltraSparc T1 processor 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (2009-06)
    Conference report
    Open Access
    Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing, ...
  • NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs 

    Seyedi, Azam; Karakostas, Vasileios; Cosemans, Stefan; Cristal Kestelman, Adrián; Nemirovsky, Mario; Unsal, Osman (Institute of Electrical and Electronics Engineers (IEEE), 2015-07-10)
    Conference report
    Open Access
    In this paper we propose a novel Content Addressable Memory (CAM) cell, NEMsCAM, based on both Nano-electro-mechanical (NEM) switches and CMOS technologies. The memory component of the proposed CAM cell is designed with ...
  • Networking challenges and prospective impact of broadcast-oriented wireless networkson- chip 

    Abadal Cavallé, Sergi; Nemirovsky, Mario; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (Association for Computing Machinery (ACM), 2015)
    Conference report
    Restricted access - publisher's policy
    The cost of broadcast has been constraining the design of manycore processors and of the algorithms that run upon them. However, as on-chip RF technologies allow the design of small-footprint and high-bandwidth antennas ...
  • On the area and energy scalability of wireless network-on-chip: a model-based benchmarked design space exploration 

    Abadal Cavallé, Sergi; Iannazzo Soteras, Mario Enrique; Nemirovsky, Mario; Cabellos Aparicio, Alberto; Lee, Heekwan; Alarcón Cot, Eduardo José (2014-07-02)
    Article
    Open Access
    Networks-on-Chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is ...
  • Overhead of the spin-lock loop in UltraSPARC T2 

    Cakarevic, Vladimir; Radojkovic, Petar; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Nemirovsky, Mario; Valero Cortés, Mateo; Pajuelo González, Manuel Alejandro; Verdú Mulà, Javier (2008-06-04)
    Conference report
    Open Access
    Spin locks are task synchronization mechanism used to provide mutual exclusion to shared software resources. Spin locks have a good performance in several situations over other synchronization mechanisms, i.e., when on ...
  • Scalability of broadcast performance in wireless network-on-chip 

    Abadal Cavallé, Sergi; Mestres Sugrañes, Albert; Nemirovsky, Mario; Lee, Heekwan; González Colás, Antonio María; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2016-12-01)
    Article
    Open Access
    Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors ...