Now showing items 1-4 of 4

    • A case study of hybrid dataflow and shared-memory programming models: Dependency-based parallel game engine 

      Gajinov, Vladimir; Eric, Igor; Stojanovic, Saa; Milutinovic, Veljko; Unsal, Osman Sabri; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference report
      Restricted access - publisher's policy
      Recently proposed hybrid dataflow and shared memory programming models combine these two underlying models in order to support a wider range of problems naturally. The effectiveness of such hybrid models for parallel ...
    • Interconnection networks in petascale computer systems: A survey 

      Trobec, Roman; Vasiljevic, Radivoje; Tomasevic, Milo; Milutinovic, Veljko; Beivide Palacio, Ramon; Valero Cortés, Mateo (2016-11)
      Article
      Restricted access - publisher's policy
      This article provides background information about interconnection networks, an analysis of previous developments, and an overview of the state of the art. The main contribution of this article is to highlight the importance ...
    • New benchmarking methodology and programming model for big data processing 

      Kos, Anton; Tomažic, Sašo; Salom, Jakob; Trifunovic, Nemanja; Valero Cortés, Mateo; Milutinovic, Veljko (2015-08)
      Article
      Open Access
      Big data processing is becoming a reality in numerous real-world applications. With the emergence of new data intensive technologies and increasing amounts of data, new computing concepts are needed. The integration of big ...
    • The ultimate dataflow for ultimate supercomputers-on-a-chip, for scientific computing, geo physics, complex mathematics, and information processing 

      Milutinovic, Veljko; Sadeqi Azer, Erfan; Yoshimoto, Kristy; Klimeck, Gerhard; Djordjevic, Miljan; Kotlar, Milos; Bojovic, Miroslav; Miladinovic, Bozidar; Korolija, Nenad; Stankovic, Stevan; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Restricted access - publisher's policy
      This paper introduces a conceptual 100BillionTransistor (100BT) SuperComputers-on-a-Chip consisting of N big multi-core processors, 1000N small many-core processors, and two hardware accelerators - an ASIC TPU-like ...