Ara es mostren els items 1-20 de 195

    • A comparison of cache hierarchies for SMT processors 

      Suárez Gracía, Dario; Monreal Arnal, Teresa; Viñals Yúfera, Víctor (Universidad de La Laguna. Servicio de Publicaciones, 2011)
      Text en actes de congrés
      Accés obert
      In the multithread and multicore era, programs are forced to share part of the processor structures. On one hand, the state of the art in multithreading describes how efficiently manage and distribute inner resources such ...
    • A complexity-effective simultaneous multithreading architecture 

      Acosta Ojeda, Carmelo Alexis; Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
      Text en actes de congrés
      Accés obert
      Different applications may exhibit radically different behaviors and thus have very different requirements in terms of hardware support. In simultaneous multithreading (SMT) architectures, the hardware is shared among ...
    • A decoupled KILO-instruction processor 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
      Text en actes de congrés
      Accés obert
      Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are ...
    • A microprocessor-based speed controller for DC motors 

      Bertran Albertí, Eduardo; Herranz, J; Martinez, L; Miguel, J; Munilla, I. (1983-07)
      Article
      Accés obert
      The introduction of microprocessors into electric vehicles has opened many interesting possibilities for improving the operation and maintenance of such automotive systems. On the other hand, microcomputer-based motor ...
    • A new countermeasure against side-channel attacks based on hardware-software co-design 

      Lumbiarres López, Rubén; López García, Mariano; Cantó Navarro, Enrique (2016-09-01)
      Article
      Accés obert
      This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which ...
    • A software-hardware hybrid steering mechanism for clustered microarchitectures 

      Cai, Qiong; Codina Viñas, Josep M.; González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2008)
      Text en actes de congrés
      Accés obert
      Clustered microarchitectures provide a promising paradigm to solve or alleviate the problems of increasing microprocessor complexity and wire delays. High- performance out-of-order processors rely on hardware-only steering ...
    • Accelerating SpMV on FPGAs through block-row compress: a task-based approach 

      Oliver Segura, José; Álvarez Martínez, Carlos; Cervero García, Teresa; Martorell Bofill, Xavier; Davis, John D.; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Comunicació de congrés
      Accés obert
      Sparse Matrix-Vector multiplication (SpMV), computing y=α⋅A×x+β⋅y where y,x are dense vectors, α,β two scalar constants, and A is a sparse matrix, is a key kernel in many HPC applications. It exhibits a kind of memory ...
    • Adaptive and application dependant runtime guided hardware reconfiguration for the IBM POWER7 

      Prat Robles, David (Universitat Politècnica de Catalunya, 2014-09-04)
      Projecte Final de Màster Oficial
      Accés obert
      The aim of this project is to develop adaptive resource management systems for the im- provement of the power-performance metrics associated with the current and future IBM POWER-series microprocessors.
    • Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM Power7 

      Prat Robles, David; Ortega Carrasco, Cristobal; Casas, Marc; Moretó Planas, Miquel; Valero Cortés, Mateo (2015)
      Text en actes de congrés
      Accés obert
    • Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability 

      Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (2012-07)
      Article
      Accés restringit per política de l'editorial
      This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure ...
    • AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures 

      Aleta Ortega, Alexandre; Codina Viñas, Josep M.; Sánchez Navarro, F. Jesús; González Colás, Antonio María; Kaeli, D (2009-06)
      Article
      Accés obert
      This paper presents AGAMOS, a technique to modulo schedule loops on clustered microarchitectures. The proposed scheme uses a multilevel graph partitioning strategy to distribute the workload among clusters and reduces the ...
    • An energy-efficient memory unit for clustered microarchitectures 

      Bieschewski, Stefan; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2016-08-01)
      Article
      Accés obert
      Whereas clustered microarchitectures themselves have been extensively studied, the memory units for these clustered microarchitectures have received relatively little attention. This article discusses some of the inherent ...
    • An ultra low-power hardware accelerator for automatic speech recognition 

      Yazdani Aminabadi, Reza; Segura Salvador, Albert; Arnau Montañés, José María; González Colás, Antonio María (IEEE Press, 2016)
      Text en actes de congrés
      Accés obert
      Automatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost which is not affordable for the tiny power budget of mobile devices. ...
    • Anàlisi i millora d’un sistema operatiu per sistemes encastats: diagnosi i adaptació d’un sistema operatiu per plataformes de desenvolupament basades en sistemes encastats 

      Mellado Cerezo, Álvaro (Universitat Politècnica de Catalunya, 2023-01-27)
      Treball Final de Grau
      Accés obert
      En aquest document, aprofundirem sobre com gestionen els serveis cada sistema operatiu i les diferències tècniques entre un MicroKernel i un Kernel monolític per tal de conèixer avantatges d’ús de cadascun. També intentarem ...
    • Aplicació dels microprocessadors software al disseny i construcció d'una calculadora 

      Galicia Sitjas, Ricard (Universitat Politècnica de Catalunya, 2014-06-11)
      Treball Final de Grau
      Accés obert
      El present treball consisteix en un estudi dels microprocessadors software, en particular de MicroBlaze, i en el disseny i implementació d’una aplicació amb MicroBlaze mitjançant la versió 12.3 de Embedded Development Kit ...
    • Archexplorer for automatic design space exploration 

      Desmet, V.; Girbal, Sylvain; Ramírez Bellido, Alejandro; Temam, Olivier; Vega, Augusto (2010-09-09)
      Article
      Accés obert
      Growing architectural complexity and stringent time-to-market constraints suggest the need to move architecture design beyond parametric exploration to structural exploration. ArchExplorer is a Web-based permanent and open ...
    • Automatic synthesis and optimization of chip multiprocessors 

      Nikitin, Nikita (Universitat Politècnica de Catalunya, 2013-04-05)
      Tesi
      Accés obert
      The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental ...
    • Automatització de testing i validació per aplicacions C en sistemes encastats 

      Grífol Álvarez, Aleix (Universitat Politècnica de Catalunya, 2018-10)
      Treball Final de Grau
      Accés restringit per decisió de l'autor
      Realitzat a/amb:   Ficosa Electronics
      En aquest treball de final de grau, es desenvoluparà una metodologia de treball amb una sèrie d'eines, que un cop integrades dins d'un projecte dedicat al desenvolupament de software, es permeti i faciliti la creació de ...
    • Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery 

      Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Text en actes de congrés
      Accés obert
      The trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling ...
    • Batec Connected 

      Cahiz Sánchez, Mario (Universitat Politècnica de Catalunya, 2016-01-08)
      Treball Final de Grau
      Accés obert
      Realitzat a/amb:   Batec Mobility
      This thesis project is based on the integration of a data collection system with multiple sensors to be displayed in real time on a mobile application for the products of Batec Mobility S.L. in order to improve the customer ...