Ara es mostren els items 1-20 de 144

  • A comparison of cache hierarchies for SMT processors 

    Suárez Gracía, Dario; Monreal Arnal, Teresa; Viñals Yúfera, Víctor (Universidad de La Laguna. Servicio de Publicaciones, 2011)
    Text en actes de congrés
    Accés obert
    In the multithread and multicore era, programs are forced to share part of the processor structures. On one hand, the state of the art in multithreading describes how efficiently manage and distribute inner resources such ...
  • A complexity-effective simultaneous multithreading architecture 

    Acosta Ojeda, Carmelo Alexis; Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Text en actes de congrés
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    Different applications may exhibit radically different behaviors and thus have very different requirements in terms of hardware support. In simultaneous multithreading (SMT) architectures, the hardware is shared among ...
  • Adaptive and application dependant runtime guided hardware reconfiguration for the IBM POWER7 

    Prat Robles, David (Universitat Politècnica de Catalunya, 2014-09-04)
    Projecte Final de Màster Oficial
    Accés obert
    The aim of this project is to develop adaptive resource management systems for the im- provement of the power-performance metrics associated with the current and future IBM POWER-series microprocessors.
  • Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM Power7 

    Prat Robles, David; Ortega, Cristobal; Casas Guix, Marc; Moreto Planas, Miquel; Valero Cortés, Mateo (2015)
    Text en actes de congrés
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  • Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability 

    Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (2012-07)
    Article
    Accés restringit per política de l'editorial
    This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure ...
  • A decoupled KILO-instruction processor 

    Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
    Text en actes de congrés
    Accés obert
    Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are ...
  • AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures 

    Aleta Ortega, Alexandre; Codina Viñas, Josep M.; Sánchez Navarro, F. Jesús; González Colás, Antonio María; Kaeli, D (2009-06)
    Article
    Accés obert
    This paper presents AGAMOS, a technique to modulo schedule loops on clustered microarchitectures. The proposed scheme uses a multilevel graph partitioning strategy to distribute the workload among clusters and reduces the ...
  • A microprocessor-based speed controller for DC motors 

    Bertran Albertí, Eduardo; Herranz, J; Martinez, L; Miguel, J; Munilla, I. (1983-07)
    Article
    Accés obert
    The introduction of microprocessors into electric vehicles has opened many interesting possibilities for improving the operation and maintenance of such automotive systems. On the other hand, microcomputer-based motor ...
  • An energy-efficient memory unit for clustered microarchitectures 

    Bieschewski, Stefan; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2016-08-01)
    Article
    Accés obert
    Whereas clustered microarchitectures themselves have been extensively studied, the memory units for these clustered microarchitectures have received relatively little attention. This article discusses some of the inherent ...
  • A new countermeasure against side-channel attacks based on hardware-software co-design 

    Lumbiarres López, Rubén; López García, Mariano; Cantó Navarro, Enrique (2016-09-01)
    Article
    Accés obert
    This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which ...
  • An ultra low-power hardware accelerator for automatic speech recognition 

    Yazdani Aminabadi, Reza; Segura Salvador, Albert; Arnau Montañés, José María; González Colás, Antonio María (IEEE Press, 2016)
    Text en actes de congrés
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    Automatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost which is not affordable for the tiny power budget of mobile devices. ...
  • Aplicació dels microprocessadors software al disseny i construcció d'una calculadora 

    Galicia Sitjas, Ricard (Universitat Politècnica de Catalunya, 2014-06-11)
    Treball Final de Grau
    Accés obert
    El present treball consisteix en un estudi dels microprocessadors software, en particular de MicroBlaze, i en el disseny i implementació d’una aplicació amb MicroBlaze mitjançant la versió 12.3 de Embedded Development Kit ...
  • Archexplorer for automatic design space exploration 

    Desmet, V.; Girbal, Sylvain; Ramírez Bellido, Alejandro; Temam, Olivier; Vega, Augusto (2010-09-09)
    Article
    Accés obert
    Growing architectural complexity and stringent time-to-market constraints suggest the need to move architecture design beyond parametric exploration to structural exploration. ArchExplorer is a Web-based permanent and open ...
  • A software-hardware hybrid steering mechanism for clustered microarchitectures 

    Cai, Qiong; Codina Viñas, Josep M.; González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Text en actes de congrés
    Accés obert
    Clustered microarchitectures provide a promising paradigm to solve or alleviate the problems of increasing microprocessor complexity and wire delays. High- performance out-of-order processors rely on hardware-only steering ...
  • Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery 

    Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Text en actes de congrés
    Accés obert
    The trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling ...
  • Batec Connected 

    Cahiz Sánchez, Mario (Universitat Politècnica de Catalunya, 2016-01-08)
    Treball Final de Grau
    Accés obert
    Realitzat a/amb:  Batec Mobility
    This thesis project is based on the integration of a data collection system with multiple sensors to be displayed in real time on a mobile application for the products of Batec Mobility S.L. in order to improve the customer ...
  • Beehive: an FPGA-based multiprocessor architecture 

    Arcas Abella, Oriol (Universitat Politècnica de Catalunya, 2009-09-23)
    Projecte Final de Màster Oficial
    Accés obert
    In recent years, to accomplish with the Moore's law hardware and software designers are tending progressively to focus their efforts on exploiting instruction-level parallelism. Software simulation has been essential for ...
  • Benchmarks en diferents microprocessadors 

    Caubet Gomà, Josep (Universitat Politècnica de Catalunya, 2006-07-19)
    Projecte/Treball Final de Carrera
    Accés obert
    The objective of this thesis is to obtain results of benchmarking between different boards; RCM3720 of Rabbit Semiconductor and SNAP and IM3000 of Imsys Technologies. Three different computer languages have been used: C, ...
  • Block disabling characterization and improvements in CMPs operating at ultra-low voltages 

    Ferrerón, Alexandra; Suárez Gracia, Darío; Alastruey, Jesús; Monreal Arnal, Teresa; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Text en actes de congrés
    Accés obert
    Power density has become the limiting factor in technology scaling as power budget restricts the amount of hardware that can be active at the same time. Reducing supply voltage to ultra-low voltage ranges close to the ...
  • Characterization and modeling of multicast communication in cache-coherent manycore processors 

    Abadal Cavallé, Sergi; Martinez, Raul; Solé Pareta, Josep; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2016-01-21)
    Article
    Accés obert
    The scalability of Network-on-Chip (NoC) designs has become a rising concern as we enter the manycore era. Multicast support represents a particular yet relevant case within this context, mainly due to the poor performance ...