Browsing by Subject "Memòria jeràrquica (Informàtica)"

Now showing items 1-7 of 7

    • Active measurement of memory resource consumption 

      Casas, Marc; Bronevetsky, Greg (IEEE, 2014)
      Conference report
      Open Access
      Hierarchical memory is a cornerstone of modern hardware design because it provides high memory performance and capacity at a low cost. However, the use of multiple levels of memory and complex cache management policies ...

    • Comparative Study of Prefetching Mechanisms 

      Torrents Lapuerta, Martí (Universitat Politècnica de Catalunya, 2009-09-23)
      Master thesis
      Restricted access - confidentiality agreement

    • Estudi de la jeràquia de memòria d'una GPU 

      Rodríguez López, Josep (Universitat Politècnica de Catalunya, 2010-06-28)
      Master thesis (pre-Bologna period)
      Restricted access - confidentiality agreement

    • Evaluation of HPC applications’ Memory Resource Consumption via Active Measurement 

      Casas, Marc; Bronevetsky, Greg (IEE, 2016)
      Article
      Open Access
      As the number of compute cores per chip continues to rise faster than the total amount of available memory, applications will become increasingly starved for memory storage capacity and bandwidth, making the problem of ...

    • Improving prefetching mechanisms for tiled CMP platforms 

      Torrents Lapuerta, Martí (Universitat Politècnica de Catalunya, 2016-11-28)
      Doctoral thesis
      Open Access
      Recently, high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures to deal with instruction level parallelism limitations and, more important, to manage the power consumption that is ...

    • Last Bank: dealing with address reuse in non-uniform cache architecture for CMPs 

      Lira Rueda, Javier; Molina Clemente, Carlos; González Colás, Antonio María (2009-01-16)
      Research report
      Open Access
      In response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latencies. This architecture divides a large memory ...

    • LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors 

      Lira Rueda, Javier; Molina Clemente, Carlos; González Colás, Antonio María (2009-05-14)
      Research report
      Open Access
      The increasing speed-gap between processor and memory and the limited memory bandwidth make last-level cache performance crucial for CMP architectures. Non Uniform Cache Architectures (NUCA) has been introduced to deal ...