Now showing items 1-14 of 14

    • Adaptive runtime-assisted block prefetching on chip-multiprocessors 

      García Flores, Víctor; Rico Carro, Alejandro; Villavieja Prados, Carlos; Carpenter, Paul M.; Navarro, Nacho; Ramirez, Alex (2016-04-29)
      Article
      Open Access
      Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the ...
    • Cache-aware load balancing vs. cooperative caching for distributed search engines 

      Domínguez Sal, David; Pérez Casany, Marta; Larriba Pey, Josep (IEEE Computer Society Publications, 2009-06-25)
      Conference report
      Open Access
      In this paper we study the performance of a distributed search engine from a data caching point of view. We compare and combine two different approaches to achieve better hit rates: (a) send the queries to the node which ...
    • Communication bottelneck analysis on big data applications 

      Roca Marí, Damián (Universitat Politècnica de Catalunya, 2013-03-07)
      Master thesis (pre-Bologna period)
      Open Access
      [ANGLÈS] Computers, and multicore processors in specific, need cache memory to improve memory bandwidth and overall performance. There are different types of cache (private and shared) divided into different levels of ...
    • Compartición de espacio entre instrucciones 

      Rodríguez Lafuente, Clemente; Viñals Yúfera, Víctor; Labarta Mancho, Jesús José (E.T.S.I. de Telecomunicación, 1985)
      Conference report
      Open Access
      Un gran número de computadores en la actualidad usan memoria cache para adaptar la velocidad de la memoria a la del procesador, o bien reducir el tráfico en sistemas multiprocesadores. En la actualidad un tema discutido ...
    • Intelligent colocation of HPC workloads 

      Vieira Zacarias, Felippe; Petrucci, Vinicius; Nishtala, Rajiv; Carpenter, Paul; Mossé, Daniel (Elsevier, 2021-05)
      Article
      Restricted access - publisher's policy
      Many server applications suffer from a bottleneck in the shared caches, instruction execution units, I/O or memory bandwidth, even though the remaining resources may be underutilized. It is hard for developers and runtime ...
    • Interleaved Scrambling Technique: A Novel Low-Power Security Layer for Cache Memories 

      Neagu, Madalin; Manich Bou, Salvador; Miclea, Liviu (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference lecture
      Restricted access - publisher's policy
      Memory systems security has increased over the last decade due to the sensitive information which is stored in plain text. Device specific attacks, such as cold-boot and sidechannel monitoring have been reported as being ...
    • Low Vccmin fault-tolerant cache with highly predictable performance 

      Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2009)
      Conference report
      Restricted access - publisher's policy
      Transistors per area unit double in every new technology node. However, the electric field density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace with new technology nodes to prevent ...
    • Near-optimal replacement policies for shared caches in multicore processors 

      Díaz Maag, Javier; Ibáñez Marín, Pablo; Monreal Arnal, Teresa; Viñals Yúfera, Victor; Llaberia Griñó, José M. (2021-03-29)
      Article
      Restricted access - publisher's policy
      An optimal replacement policy that minimizes the miss rate in a private cache was proposed several decades ago. It requires knowing the future access sequence the cache will receive. There is no equivalent for shared caches ...
    • On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-12-05)
      External research report
      Restricted access - publisher's policy
      In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive ...
    • Reusing cached schedules in an out-of-order processor with in-order issue logic 

      Palomar Pérez, Óscar; Juan, Toni; Navarro Guerrero, Juan José (2009)
      Conference report
      Open Access
      The complex and powerful out-of-order issue logic dismisses the repetitive nature of the code, unlike what caches or branch predictors do. We show that 90% of the cycles, the group of instructions selected by the issue ...
    • Smart memory management through locality analysis 

      Sánchez Navarro, Francisco Jesús (Universitat Politècnica de Catalunya, 2001-11-06)
      Doctoral thesis
      Open Access
      Las memorias caché fueron incorporadas en los microprocesadores ya desde los primeros tiempos, y representan la solución más común para tratar la diferencia de velocidad entre el procesador y la memoria. Sin embargo, muchos ...
    • Software caching techniques and hardware optimizations for on-chip local memories 

      Vujic, Nikola (Universitat Politècnica de Catalunya, 2012-06-05)
      Doctoral thesis
      Open Access
      Despite the fact that the most viable L1 memories in processors are caches, on-chip local memories have been a great topic of consideration lately. Local memories are an interesting design option due to their many benefits: ...
    • VIPS: simple, efficient, and scalable cache coherence 

      Ros, Alberto (Barcelona Supercomputing Center, 2016-09-10)
      External research report
      Open Access
      Directory-based cache coherence is the de-facto standard for scalable shared-memory multi/many-cores and significant effort is invested in reducing its overhead. However, directory area and complexity optimizations are ...
    • WiDir: A Wireless-Enabled Directory cache coherence protocol 

      Franques, Antonio; Kokolis, Apostolos; Abadal Cavallé, Sergi; Fernando, Vimuth; Misailovic, Sasa; Torrellas, Josep (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      As the core count in shared-memory manycores keeps increasing, it is becoming increasingly harder to design cache-coherence protocols that deliver high performance without an inordinate increase in complexity and cost. In ...