Browsing by Author "Meenderinck, Cor"

Now showing items 1-8 of 8

    • A highly scalable parallel implementation of H.264 

      Azevedo, Arnaldo; Juurlink, Ben; Meenderinck, Cor; Terechko, Andrei; Hoogerbrugge, Jan; Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2011)
      Article
      Open Access
      Developing parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation ...

    • Parallel H.264 decoding on an embedded multicore processor 

      Azevedo, Arnaldo; Meenderinck, Cor; Juurlink, Ben; Terechko, Andrei; Hoogerbrugge, Jan; Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro (Springer-Verlag, Berlin, Heidelberg,, 2009-01-28)
      Conference report
      Restricted access - publisher's policy
      In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inter-frame dependencies have a limited spatial ...

    • Parallel scalability of video decoders 

      Meenderinck, Cor; Azevedo, Arnaldo; Juurlink, Ben; Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro (2009-11)
      Article
      Restricted access - publisher's policy
      An important question is whether emerging and future applications exhibit sufficient parallelism, in particular thread-level parallelism, to exploit the large numbers of cores future chip multiprocessors (CMPs) are ...

    • Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture 

      Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Azevedo, Arnaldo; Meenderinck, Cor; Juurlink, Ben (2009-06)
      Article
      Restricted access - publisher's policy
      Este artículo presenta un estudio de la escalabilidad del rendimiento en el paralelismo a nivel macro bloque de un decodificador H.264 para aplicaciones de alta definición (HD) en arquitecturas de múltiples procesadores. ...

    • Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture 

      Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Azevedo, Arnaldo; Meenderinck, Cor; Juurlink, Ben (2009-04-23)
      Conference report
      Restricted access - publisher's policy
      This paper presents a study of the performance scalability of a macroblock-level parallelization of the H.264 decoder for High De nition (HD) applications on a multiprocessor architecture. We have implemented this ...

    • Scalability of Macroblock-level parallelism for H.264 decoding 

      Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro; Azevedo, Arnaldo; Meenderinck, Cor; Juurlink, Ben; Valero Cortés, Mateo (IEEE Computer Society Publications, 2009-12-11)
      Conference report
      Open Access
      This paper investigates the scalability of MacroBlock(MB) level parallelization of the H.264 decoder for High Definition (HD) applications. The study includes three parts. First, a formal model for predicting the maximum ...

    • Scalability of parallel video decoding on heterogeneous manycore architectures 

      Álvarez Mesa, Mauricio; Cabarcas Jaramillo, Felipe; Ramírez Bellido, Alejandro; Meenderinck, Cor; Juurlink, Ben; Valero Cortés, Mateo (2011)
      Research report
      Open Access
      This paper presents an analysis of the scalability of the parallel video decoding on heterogeneous many core architectures. As benchmark, we use a highly parallel H.264/AVC video decoder that generates a large number of ...

    • The SARC architecture 

      Gaydadjiev, Georgi; Isaza, Sebastian; Ramírez Bellido, Alejandro; Cabarcas, Felipe; Juurlink, Ben; Álvarez Mesa, Mauricio; Sánchez Castaño, Friman; Azevedo, Arnaldo; Meenderinck, Cor; Ciobanu, Catalin (2010-10)
      Article
      Open Access
      The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically ...