Now showing items 1-20 of 55

    • A class of stable nonlinear systems for modelling memory effects in RF power amplifiers 

      Montoro López, Gabriel; Gilabert Pinal, Pere Lluís; Berenguer Sau, Jordi; Bertran Albertí, Eduardo (Escuela Politécnica Superior Ingeniería Gijón, 2006)
      Conference report
      Open Access
    • A generator of numerically-tailored and high-throughput accelerators for batched GEMMs 

      Ledoux Pardo, Luis Eduardo; Casas Guix, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Conference report
      Open Access
      We propose a hardware generator of GEMM accelerators. Our generator produces vendor-agnostic HDL describing highly customizable systolic arrays guided by accuracy and energy efficiency goals. The generated arrays have three ...
    • A hardware runtime for task-based programming models 

      Tan, Xubin; Bosch, Jaume; Álvarez, Carlos; Jiménez González, Daniel; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2019-09-01)
      Article
      Open Access
      Task-based programming models such as OpenMP 5.0 and OmpSs are simple to use and powerful enough to exploit task parallelism of applications over multicore, manycore and heterogeneous systems. However, their software-only ...
    • A hardware/software co-design of K-mer counting using a CAPI-enabled FPGA 

      Haghi, Abbas; Álvarez Martí, Lluc; Polo Bardés, Jorda; Diamantopoulos, Dionysios; Hagleitner, Christoph; Moreto Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      Advances in Next Generation Sequencing (NGS) technologies have caused the proliferation of genomic applications to detect DNA mutations and guide personalized medicine. These applications have an enormous computational ...
    • A hierarchical mathematical model for automatic pipelining and allocation using elastic systems 

      Cortadella, Jordi; Petit Silvestre, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Conference report
      Open Access
      The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ...
    • A method for real-time generation of slew-rate limited envelopes in envelope tracking transmitters 

      Montoro López, Gabriel; Gilabert Pinal, Pere Lluís; Bertran Albertí, Eduardo; Berenguer Sau, Jordi (2010-02)
      Conference report
      Open Access
    • A novel FPGA-based high throughput accelerator for binary search trees 

      Melikoglu, Oyku; Ergin, Oguz; Salami, Behzad; Pavón Rivera, Julián; Unsal, Osman Sabri; Cristal Kestelman, Adrián (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      This paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) ...
    • A template system for the efficient compilation of domain abstractions onto reconfigurable computers 

      Shafiq, Muhammad; Pericàs Gleim, Miquel; Ayguadé Parra, Eduard (2011)
      Conference report
      Restricted access - publisher's policy
      Past research has addressed the issue of using FPGAs as accelerators for HPC systems. However, writing low level code for an efficient, portable and scalable architecture altogether has been always a ...
    • Advanced pattern based memory controller for FPGA based HPC applications 

      Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference report
      Restricted access - publisher's policy
      The ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which ...
    • Aggressive undervolting of FPGAs : power & reliability trade-offs 

      Salami, Behzad (Universitat Politècnica de Catalunya, 2018-11-19)
      Doctoral thesis
      Open Access
      In this work, we evaluate aggressive undervolting, i.e., voltage underscaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by ...
    • AMC: Advanced Multi-accelerator Controller 

      Hussain, Tassadaq; Haider, Amna; Gursal, Shakaib A.; Ayguadé Parra, Eduard (2015-01)
      Article
      Open Access
      The rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS ...
    • AMMC: advance multi-core memory controller 

      Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference lecture
      Open Access
      In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ...
    • An academic RISC-V silicon implementation based on open-source components 

      Abella Ferrer, Jaume; Bulla, Calvin; Cabo Pitarch, Guillem; Cazorla Almeida, Francisco Javier; Cristal Kestelman, Adrián; Doblas Font, Max; Figueras Bagué, Roger; González Trejo, Alberto; Hernández Luz, Carles; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kosmidis, Leonidas; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Marimon Illana, Joan; Martínez Martínez, Ricardo; Mendoza Escobar, Jonnatan; Moll Echeto, Francisco de Borja; Moreto Planas, Miquel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Ramírez Salinas, Marco Antonio; Rojas Morales, Carlos; Rubio Sola, Jose Antonio; Ruiz, Abraham Josafat; Sonmez, Nehir; Soria Pardos, Víctor; Teres Teres, Lluis; Unsal, Osman Sabri; Valero Cortés, Mateo; Vargas Valdivieso, Iván; Villa Vargas, Luis Alfonso (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ...
    • An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration 

      Salami, Behzad; Onural, Erhan Baturay; Yuksel, Ismail Emir; Koc, Fahrettin; Ergin, Oguz; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Sarbazi-Azad, Hamid; Mutlu, Onur (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field ...
    • An FPGA accelerator of the wavefront algorithm for genomics pairwise alignment 

      Haghi, Abbas; Marco-Sola, Santiago; Álvarez Martí, Lluc; Diamantopoulos, Dionysios; Hagleitner, Christoph; Moreto Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      In the last years, advances in next-generation sequencing technologies have enabled the proliferation of genomic applications that guide personalized medicine. These applications have an enormous computational cost due to ...
    • Anàlisi de la interconnexió de dispositius lògics programables mitjançant Ethernet 

      Peshevski, Marko (Universitat Politècnica de Catalunya, 2017-02-09)
      Master thesis
      Restricted access - author's decision
      En aquest treball s'estudia com fer funcionar Ethernet des d'una placa amb FPGA (de l'anglès Field Programmable Gate Array). Aquests són dispositius electrònics que permeten reprogramar la lògica que contenen dins per ...
    • Aplicación de técnicas avanzadas de lienalización a sistemas de RF/microondas 

      García, J.A.; Bertran Albertí, Eduardo; Begrains, J.; Montoro López, Gabriel; Ares, F.; Cabria, L. (Editorial de la UPV, 2005)
      Conference report
      Open Access
    • Application Acceleration on FPGAs with OmpSs@FPGA 

      Bosch, Jaume; Tan, Xubin; Filgueras Izquierdo, Antonio; Vidal, Miquel; Mateu, Marc; Jiménez-González, Daniel; Álvarez, Carlos; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      OmpSs@FPGA is the flavor of OmpSs that allows offloading application functionality to FPGAs. Similarly to OpenMP, it is based on compiler directives. While the OpenMP specification also includes support for heterogeneous ...
    • AXIOM: a hardware-software platform for cyber physical systems 

      Mazumdar, Somnath; Ayguadé Parra, Eduard; Bettin, Nicola; Bueno Hedo, Javier; Ermini, Sara; Filgueras Izquierdo, Antonio; Jiménez González, Daniel; Álvarez Martínez, Carlos; Martorell Bofill, Xavier; Montefoschi, Francesco; Oro Garcia, David; Pnevmatikatos, Dionisis; Rizzo, Antonio; Theodoropoulos, Dimitris; Giorgi, Roberto (2016)
      Conference report
      Restricted access - publisher's policy
      Cyber-Physical Systems (CPSs) are widely necessary for many applications that require interactions with the humans and the physical environment. A CPS integrates a set of hardware-software components to distribute, execute ...
    • Considerations in using OpenCL on GPUs and FPGAs for throughput-oriented genomics workloads 

      Cadenelli, Nicola; Jaksic, Zoran; Polo Bardés, Jordà; Carrera Pérez, David (Elsevier, 2019-05)
      Article
      Open Access
      The recent upsurge in the available amount of health data and the advances in next-generation sequencing are setting the ground for the long-awaited precision medicine. To process this deluge of data, bioinformatics workloads ...