Browsing by Subject "Matrius de portes programables per l'usuari"
Now showing items 1-20 of 63
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A class of stable nonlinear systems for modelling memory effects in RF power amplifiers
(Escuela Politécnica Superior Ingeniería Gijón, 2006)
Conference report
Open Access -
A generator of numerically-tailored and high-throughput accelerators for batched GEMMs
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessWe propose a hardware generator of GEMM accelerators. Our generator produces vendor-agnostic HDL describing highly customizable systolic arrays guided by accuracy and energy efficiency goals. The generated arrays have three ... -
A hardware runtime for task-based programming models
(2019-09-01)
Article
Open AccessTask-based programming models such as OpenMP 5.0 and OmpSs are simple to use and powerful enough to exploit task parallelism of applications over multicore, manycore and heterogeneous systems. However, their software-only ... -
A hardware/software co-design of K-mer counting using a CAPI-enabled FPGA
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessAdvances in Next Generation Sequencing (NGS) technologies have caused the proliferation of genomic applications to detect DNA mutations and guide personalized medicine. These applications have an enormous computational ... -
A hierarchical mathematical model for automatic pipelining and allocation using elastic systems
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Open AccessThe advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ... -
A method for real-time generation of slew-rate limited envelopes in envelope tracking transmitters
(2010-02)
Conference report
Open Access -
A novel FPGA-based high throughput accelerator for binary search trees
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference report
Open AccessThis paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) ... -
A template system for the efficient compilation of domain abstractions onto reconfigurable computers
(2011)
Conference report
Restricted access - publisher's policyPast research has addressed the issue of using FPGAs as accelerators for HPC systems. However, writing low level code for an efficient, portable and scalable architecture altogether has been always a ... -
Advanced pattern based memory controller for FPGA based HPC applications
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Restricted access - publisher's policyThe ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which ... -
Aggressive undervolting of FPGAs : power & reliability trade-offs
(Universitat Politècnica de Catalunya, 2018-11-19)
Doctoral thesis
Open AccessIn this work, we evaluate aggressive undervolting, i.e., voltage underscaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by ... -
AIG transformations to improve LUT mapping for FPGAs
(Universitat Politècnica de Catalunya, 2022-06-28)
Master thesis
Open AccessA Field-Programmable Gate Array (FPGA) is a general re-configurable device for implementing logic circuits. This technology is extensively used for prototyping circuits due to its cost and speed. The underlying implementation ... -
AMC: Advanced Multi-accelerator Controller
(2015-01)
Article
Open AccessThe rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS ... -
AMMC: advance multi-core memory controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference lecture
Open AccessIn this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ... -
An academic RISC-V silicon implementation based on open-source components
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ... -
An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessWe empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field ... -
An FPGA accelerator of the wavefront algorithm for genomics pairwise alignment
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessIn the last years, advances in next-generation sequencing technologies have enabled the proliferation of genomic applications that guide personalized medicine. These applications have an enormous computational cost due to ... -
Anàlisi de la interconnexió de dispositius lògics programables mitjançant Ethernet
(Universitat Politècnica de Catalunya, 2017-02-09)
Master thesis
Restricted access - author's decisionEn aquest treball s'estudia com fer funcionar Ethernet des d'una placa amb FPGA (de l'anglès Field Programmable Gate Array). Aquests són dispositius electrònics que permeten reprogramar la lògica que contenen dins per ... -
Aplicación de técnicas avanzadas de lienalización a sistemas de RF/microondas
(Editorial de la UPV, 2005)
Conference report
Open Access -
Application acceleration on FPGAs with OmpSs@FPGA
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference report
Open AccessOmpSs@FPGA is the flavor of OmpSs that allows offloading application functionality to FPGAs. Similarly to OpenMP, it is based on compiler directives. While the OpenMP specification also includes support for heterogeneous ... -
AXIOM: a hardware-software platform for cyber physical systems
(2016)
Conference report
Restricted access - publisher's policyCyber-Physical Systems (CPSs) are widely necessary for many applications that require interactions with the humans and the physical environment. A CPS integrates a set of hardware-software components to distribute, execute ...
