Browsing by Author "Martínez, Alejandro"

Now showing items 1-5 of 5

    • Analysis and optimization of engines for dynamically typed languages 

      Dot Artigas, Gem; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Conference report
      Restricted access - publisher's policy
      Dynamically typed programming languages have become very popular in the recent years. These languages ease the task of the programmer but introduce significant overheads since assumptions about the types of variables have ...

    • Assisting static compiler vectorization with a speculative dynamic vectorizer in an HW/SW codesigned environment 

      Kumar, Rakesh; Martínez, Alejandro; González Colás, Antonio María (2016-01-01)
      Article
      Open Access
      Compiler-based static vectorization is used widely to extract data-level parallelism from computation-intensive applications. Static vectorization is very effective in vectorizing traditional array-based applications. ...

    • Dynamic selective devectorization for efficient power gatting of SIMD units in a HW/SW co-designed enviromment 

      Kumar, Rakesh; Martínez, Alejandro; González Colás, Antonio María (IEEE Computer Society Publications, 2013)
      Conference report
      Open Access
      Leakage power is a growing concern in current and future microprocessors. Functional units of microprocessors are responsible for a major fraction of this power. Therefore, reducing functional unit leakage has received ...

    • HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation 

      Kumar, Rakesh; Cano, José; Brankovic, Aleksandar; Pavlou, Demos; Stavrou, Kyriakos; Gibert Codina, Enric; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Conference report
      Open Access
      Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. ...

    • Quantitative characterization of the software layer of a HW/SW co-designed processor 

      Cano Reyes, José; Kumar, Rakesh; Brankovic, Aleksandar; Pavlou, Demos; Stavrou, Kyriakos; Gibert Codina, Enric; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary ...