Now showing items 1-2 of 2

    • An energy-efficient and scalable eDRAM-based register file architecture for GPGPU 

      Jing, Naifeng; Shen, Yao; Lu, Yao; Ganapathy, Shrikanth; Mao, Zhigang; Guo, Minyi; Canal Corretger, Ramon; Liang, Xiaoyao (ACM, 2013)
      Conference report
      Restricted access - publisher's policy
      The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for ...
    • Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability 

      Liang, Xiaoyao; Canal Corretger, Ramon; Wei, Gu-Yeon (2008-02)
      Open Access
      With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the ...