Browsing by Author "Kondratyev, Alex"
Now showing items 1-20 of 32
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A region-based theory for state assignment in speed-independent circuits
(1997-08)
Article
Open AccessState assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair ... -
A symbolic algorithm for the synthesis of bounded Petri nets
(Springer, 2008)
Conference report
Open AccessThis paper presents an algorithm for the synthesis of bounded Petri nets from transition systems. A bounded Petri net is always provided in case it exists. Otherwise, the events are split into several transitions to guarantee ... -
Automatic synthesis and optimization of partially specified asynchronous systems
(Association for Computing Machinery (ACM), 1999)
Conference report
Open AccessA method for automating the synthesis of asynchronous control circuits from high level (CSP-like) and/or partial STG (involving only functionally critical events) specifications is presented. The method solves two key ... -
Behavioral transformations to increase the noise immunity of asynchronous specifications
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessNoise immunity is becoming one of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the problems originated by simultaneous switching ... -
Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessTwo trends are of major concern for digital circuit designers: the relative increase of interconnect delays with respect to gate delays and the demand for design reuse. Both pose difficult problems to synchronous design ... -
Checking signal transition graph implementability by symbolic bdd traversal
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Conference report
Open AccessThis paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification ... -
Complete state encoding based on the theory of regions
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Conference report
Open AccessSynthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which ... -
Coping with the variability of combinational logic delays
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Conference report
Open AccessThis paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead ... -
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(1999-09)
Article
Open AccessThis paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available ... -
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessPresents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in ... -
Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
(2006-10)
Article
Open AccessAsynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design ... -
Formal verification of safety properties in timed circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Conference report
Open AccessThe incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed stare space, a conservative ... -
From synchronous to asynchronous: an automatic approach
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Conference report
Open AccessThis paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case study shows the applicability of the method ... -
Handshake protocols for de-synchronization
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Conference report
Open AccessDe-synchronization appears as a new paradigm to automate the design of asynchronous circuits from synchronous netlists. This paper studies different protocols for de-synchronization and formally proves their correctness. ... -
Hardware and Petri nets: application to asynchronous circuit design
(Springer, 2000-06)
Article
Open AccessAsynchronous circuits is a discipline in which the theory of concurrency is applied to hardware design. This paper presents an overview of a design framework in which Petri nets are used as the main behavioral model for ... -
Identifying state coding conflicts in asynchronous system specifications using Petri net unfoldings
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Conference report
Open AccessState coding conflict detection is a fundamental part of synthesis of asynchronous concurrent systems from their specifications as signal transition graphs (STGs), which are a special kind of labelled Petri nets. The paper ... -
Lazy transition systems and asynchronous circuits synthesis with relative timing assumptions
(2002-02)
Article
Open AccessThis paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness ... -
Lazy transition systems: application to timing optimization of asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Conference report
Open AccessThe paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the ... -
Logic decomposition of speed-independent circuits
(1999-02)
Article
Open AccessLogic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional ... -
Methodology and tools for state encoding in asynchronous circuit synthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Conference report
Open AccessThis paper proposes a state encoding method for asynchronous circuits based on the theory of regions. A region in a Transition System is a set of states that “behave uniformly” with respect to a given transition (value ...
