Browsing by Author "Kishinevsky, Michael"
Now showing items 1-20 of 36
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A general model for performance optimization of sequential systems
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Conference report
Open AccessRetiming, c-slow retiming and recycling are different transformations for the performance optimization of sequential circuits. For retiming and c-slow retiming, different models that provide exact solutions have already ... -
A recursive paradigm to solve boolean relations
(Institute of Electrical and Electronics Engineers (IEEE), 2009-04)
Article
Open AccessA Boolean relation can specify some types of flexibility of a combinational circuit that cannot be expressed with don't cares. Several problems in logic synthesis, such as Boolean decomposition or multilevel minimization, ... -
A region-based algorithm for discovering Petri nets from event logs
(Springer, 2008)
Conference report
Open AccessThe paper presents a new method for the synthesis of Petri nets from event logs in the area of Process Mining. The method derives a bounded Petri net that over-approximates the behavior of an event log. The most important ... -
A region-based theory for state assignment in speed-independent circuits
(1997-08)
Article
Open AccessState assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair ... -
A symbolic algorithm for the synthesis of bounded Petri nets
(Springer, 2008)
Conference report
Open AccessThis paper presents an algorithm for the synthesis of bounded Petri nets from transition systems. A bounded Petri net is always provided in case it exists. Otherwise, the events are split into several transitions to guarantee ... -
Automatic microarchitectural pipelining
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Conference report
Open AccessThis paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct transformations including conversion to a synchronous ... -
Automatic synthesis and optimization of partially specified asynchronous systems
(Association for Computing Machinery (ACM), 1999)
Conference report
Open AccessA method for automating the synthesis of asynchronous control circuits from high level (CSP-like) and/or partial STG (involving only functionally critical events) specifications is presented. The method solves two key ... -
CAD directions for high performance asynchronous circuits
(Association for Computing Machinery (ACM), 1999)
Conference report
Open AccessThis paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 ... -
Checking signal transition graph implementability by symbolic bdd traversal
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Conference report
Open AccessThis paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification ... -
Complete state encoding based on the theory of regions
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Conference report
Open AccessSynthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which ... -
Correct-by-construction microarchitectural pipelining
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Conference report
Open AccessThis paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. Our method combines previously known bypass and retiming transformations ... -
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessPresents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in ... -
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(1999-09)
Article
Open AccessThis paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available ... -
Deriving Petri nets from finite transition systems
(Institute of Electrical and Electronics Engineers (IEEE), 1998-08)
Article
Open AccessThis paper presents a novel method to derive a Petri net from any specification model that can be mapped into a state-based representation with arcs labeled with symbols from an alphabet of events (a Transition System, ... -
Elastic circuits
(2009-10)
Article
Open AccessElasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with ... -
Elastic systems
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Conference report
Open AccessElastic systems provide tolerance to the variations in computation and communication delays. The incorporation of elasticity opens new opportunities for optimization using new correct-by-construction transformations that ... -
Elasticity and Petri nets
(2008-01)
Article
Open AccessDigital electronic systems typically use synchronous clocks and primarily assume fixed duration of their operations to simplify the design process. Time elastic systems can be constructed either by replacing the clock with ... -
Genet: a tool for the synthesis and mining of Petri nets
(Institute of Electrical and Electronics Engineers (IEEE), 2009)
Conference report
Open AccessState-based representations of concurrent systems suffer from the well known state explosion problem. In contrast, Petri nets are good models for this type of systems both in terms of complexity of the analysis and in ... -
Hardware and Petri nets: application to asynchronous circuit design
(Springer, 2000-06)
Article
Open AccessAsynchronous circuits is a discipline in which the theory of concurrency is applied to hardware design. This paper presents an overview of a design framework in which Petri nets are used as the main behavioral model for ... -
Identifying state coding conflicts in asynchronous system specifications using Petri net unfoldings
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Conference report
Open AccessState coding conflict detection is a fundamental part of synthesis of asynchronous concurrent systems from their specifications as signal transition graphs (STGs), which are a special kind of labelled Petri nets. The paper ...
